From patchwork Mon May 13 20:54:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2560491 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 315333FC5A for ; Mon, 13 May 2013 21:00:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1077AE5F73 for ; Mon, 13 May 2013 14:00:01 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f48.google.com (mail-yh0-f48.google.com [209.85.213.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 2ED7CE5DBA for ; Mon, 13 May 2013 13:54:45 -0700 (PDT) Received: by mail-yh0-f48.google.com with SMTP id f35so1643466yha.35 for ; Mon, 13 May 2013 13:54:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=LJpQXLT14yTuHN1PH22Dpl7KK8sS0ZulPPqJIAiGEGo=; b=E8TQB1ac4Zz05zDlr6EMM56z5uEuEWrXhf1C7ehA5fpmMiq0DWx15PmrKXFNJ/AA3z oR2CeZNYObWBaKR3ryHlu8eJfInmn7B91Xxk7Bs4pwdGDSAtgpnyHAlUAVVlgYPMOyMz dp3/O9U9vW9DacBAme7dE6x8HNbUdWeEK3f8VuDLfDg3R3J73skZHjEP229qZsnDsTUs Ezgk69ODr4XQCdqaB2T9TLtKzZp1xPUVzWisb8fOJ1LIEK5tL0Ossn4ymm7nAsRwc1Sy esx/Yzyn3XTjRlhq3kIeAQwF72xPNyPnHaW6/LvZjwiqo4CpEi4nuX0sIySup/CrX9AM fQJQ== X-Received: by 10.236.188.36 with SMTP id z24mr16015001yhm.96.1368478484784; Mon, 13 May 2013 13:54:44 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPSA id v27sm2295016yhk.5.2013.05.13.13.54.39 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 13 May 2013 13:54:44 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 13 May 2013 17:54:12 -0300 Message-Id: <1368478452-22470-2-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1368478452-22470-1-git-send-email-rodrigo.vivi@gmail.com> References: <1368478452-22470-1-git-send-email-rodrigo.vivi@gmail.com> Subject: [Intel-gfx] [PATCH 2/2 i-g-t] intel_chipset: Adding more reserved PCI IDs for Haswell. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. References: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi --- lib/intel_chipset.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 2cf895a..adc9233 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -97,6 +97,12 @@ #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ #define PCI_CHIP_HASWELL_S_GT2 0x041A #define PCI_CHIP_HASWELL_S_GT3 0x042A +#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ +#define PCI_CHIP_HASWELL_B_GT2 0x041B +#define PCI_CHIP_HASWELL_B_GT3 0x042B +#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ +#define PCI_CHIP_HASWELL_E_GT2 0x041E +#define PCI_CHIP_HASWELL_E_GT3 0x042E #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 @@ -106,6 +112,12 @@ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A +#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ +#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B +#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B +#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ +#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 @@ -115,6 +127,12 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A +#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ +#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B +#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B +#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ +#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E +#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 @@ -124,6 +142,12 @@ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A +#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ +#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B +#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B +#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ +#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E +#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ #define PCI_CHIP_VALLEYVIEW_1 0x0f31 @@ -210,40 +234,63 @@ #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ (devid) == PCI_CHIP_HASWELL_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_E_GT1 || \ (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT1) + (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ (devid) == PCI_CHIP_HASWELL_M_GT2 || \ (devid) == PCI_CHIP_HASWELL_S_GT2 || \ + (devid) == PCI_CHIP_HASWELL_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_E_GT2 || \ (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ + (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ + (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT2) + (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ + (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ - (devid) == PCI_CHIP_HASWELL_GT3 || \ (devid) == PCI_CHIP_HASWELL_M_GT3 || \ (devid) == PCI_CHIP_HASWELL_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_E_GT3 || \ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT3) + (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ IS_HSW_GT2(devid) || \