diff mbox

[4/6] drm/i915: fetch PCH PLL state at init time v3

Message ID 1368576511-10675-5-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes May 15, 2013, 12:08 a.m. UTC 
We need to properly track PCH PLL sharing configs, and generally set up
PCH PLL state at init time as part of the state readout process.

v2: update to new code, use intel_crtc instead (Jesse)
v3: move pll_get call to setup_hw_state (Daniel)

I-told-you-so-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   45 ++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 604f538..d03b6b0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7016,6 +7016,49 @@  static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 	pipe_config->adjusted_mode.clock = clock.dot;
 }
 
+static void ironlake_crtc_pll_get(struct intel_crtc *crtc)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 dpll_sel;
+
+	if (HAS_PCH_IBX(dev_priv->dev))
+		crtc->pch_pll = &dev_priv->pch_plls[crtc->pipe];
+
+	if (HAS_PCH_CPT(dev_priv->dev)) {
+		dpll_sel = I915_READ(PCH_DPLL_SEL);
+
+		switch (crtc->pipe) {
+		case PIPE_A:
+			if ((dpll_sel & TRANSA_DPLL_ENABLE) &&
+			    (dpll_sel & TRANSA_DPLLB_SEL))
+				crtc->pch_pll = &dev_priv->pch_plls[1];
+			else if (dpll_sel & TRANSA_DPLL_ENABLE)
+				crtc->pch_pll = &dev_priv->pch_plls[0];
+			break;
+		case PIPE_B:
+			if ((dpll_sel & TRANSB_DPLL_ENABLE) &&
+			    (dpll_sel & TRANSB_DPLLB_SEL))
+				crtc->pch_pll = &dev_priv->pch_plls[1];
+			else if (dpll_sel & TRANSB_DPLL_ENABLE)
+				crtc->pch_pll = &dev_priv->pch_plls[0];
+			break;
+		case PIPE_C:
+			if ((dpll_sel & TRANSC_DPLL_ENABLE) &&
+			    (dpll_sel & TRANSC_DPLLB_SEL))
+				crtc->pch_pll = &dev_priv->pch_plls[1];
+			else if (dpll_sel & TRANSC_DPLL_ENABLE)
+				crtc->pch_pll = &dev_priv->pch_plls[0];
+			break;
+		default:
+			BUG();
+		}
+	}
+
+	crtc->pch_pll->refcount++;
+	crtc->pch_pll->active = 1;
+}
+
 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
 				    struct intel_crtc_config *pipe_config)
 {
@@ -9684,6 +9727,8 @@  setup_pipes:
 				encoder->get_config(encoder, &crtc->config);
 				dev_priv->display.get_clock(crtc,
 							    &crtc->config);
+				if (HAS_PCH_SPLIT(dev))
+					ironlake_crtc_pll_get(crtc);
 				crtc->base.mode.clock =
 					crtc->config.adjusted_mode.clock;
 				crtc->base.mode.flags |=