From patchwork Wed May 15 00:08:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 2569161 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id E92CADF24C for ; Wed, 15 May 2013 00:10:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3060E61D2 for ; Tue, 14 May 2013 17:10:43 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy12-pub.bluehost.com (oproxy12-pub.bluehost.com [50.87.16.10]) by gabe.freedesktop.org (Postfix) with SMTP id D440EE60A2 for ; Tue, 14 May 2013 17:08:40 -0700 (PDT) Received: (qmail 3765 invoked by uid 0); 15 May 2013 00:08:40 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy12.bluehost.com with SMTP; 15 May 2013 00:08:40 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=nPgEbrnBM7/NA3DA8k50XNraN/A028rBe/VLvi4b4Y8=; b=s972V3RZxi+axs5gWQGfZBTjfKmm45GQhFLSk1nxfE3hNezpZtcToRf/OSHR7FC3g491zG5TzIK95qBNfd8bniUcYiLhmY00N9GE4zPwhDCwNM2e86bBcT4w+/ZwmK4C; Received: from [192.55.60.135] (port=11667 helo=jbarnes-t420.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1UcPGq-00014J-Ju for intel-gfx@lists.freedesktop.org; Tue, 14 May 2013 18:08:40 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Tue, 14 May 2013 17:08:29 -0700 Message-Id: <1368576511-10675-5-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368576511-10675-1-git-send-email-jbarnes@virtuousgeek.org> References: <1368576511-10675-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 192.55.60.135 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 4/6] drm/i915: fetch PCH PLL state at init time v3 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need to properly track PCH PLL sharing configs, and generally set up PCH PLL state at init time as part of the state readout process. v2: update to new code, use intel_crtc instead (Jesse) v3: move pll_get call to setup_hw_state (Daniel) I-told-you-so-by: Daniel Vetter Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 45 ++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 604f538..d03b6b0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7016,6 +7016,49 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, pipe_config->adjusted_mode.clock = clock.dot; } +static void ironlake_crtc_pll_get(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 dpll_sel; + + if (HAS_PCH_IBX(dev_priv->dev)) + crtc->pch_pll = &dev_priv->pch_plls[crtc->pipe]; + + if (HAS_PCH_CPT(dev_priv->dev)) { + dpll_sel = I915_READ(PCH_DPLL_SEL); + + switch (crtc->pipe) { + case PIPE_A: + if ((dpll_sel & TRANSA_DPLL_ENABLE) && + (dpll_sel & TRANSA_DPLLB_SEL)) + crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSA_DPLL_ENABLE) + crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + case PIPE_B: + if ((dpll_sel & TRANSB_DPLL_ENABLE) && + (dpll_sel & TRANSB_DPLLB_SEL)) + crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSB_DPLL_ENABLE) + crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + case PIPE_C: + if ((dpll_sel & TRANSC_DPLL_ENABLE) && + (dpll_sel & TRANSC_DPLLB_SEL)) + crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSC_DPLL_ENABLE) + crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + default: + BUG(); + } + } + + crtc->pch_pll->refcount++; + crtc->pch_pll->active = 1; +} + static void ironlake_crtc_clock_get(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config) { @@ -9684,6 +9727,8 @@ setup_pipes: encoder->get_config(encoder, &crtc->config); dev_priv->display.get_clock(crtc, &crtc->config); + if (HAS_PCH_SPLIT(dev)) + ironlake_crtc_pll_get(crtc); crtc->base.mode.clock = crtc->config.adjusted_mode.clock; crtc->base.mode.flags |=