From patchwork Fri May 31 15:48:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2644701 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 21D7E3FD2B for ; Fri, 31 May 2013 15:48:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 07300E615A for ; Fri, 31 May 2013 08:48:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f169.google.com (mail-ea0-f169.google.com [209.85.215.169]) by gabe.freedesktop.org (Postfix) with ESMTP id BA4BBE5CF3 for ; Fri, 31 May 2013 08:48:37 -0700 (PDT) Received: by mail-ea0-f169.google.com with SMTP id m14so1838315eaj.28 for ; Fri, 31 May 2013 08:48:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=ljq6mts3FSwZH4MdjFtnhy0kwHGDXW1+Magac8neYJY=; b=By+aaOtdEYt3eZH7jcous4KFkIxhgLLWnfeT3+MgAqVW4CEf7srdfN6/fL3BY5vxzc rTwKnbZyy8aLCtE+P177h2Tf9DKZwDeNWSz3I4Q/PstwHb+/80d7OlwgMb8zC+R0C3oS wheFj5UAjxjW6UPAnb8vQaBzama8VWUpqJ0mo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ljq6mts3FSwZH4MdjFtnhy0kwHGDXW1+Magac8neYJY=; b=iE9mPmM1bgs1mRIsRpWwOa7MceqmxkMVtyvI8vQCtQKnvs4jum5OK7uZuRTd+/EIaJ sgZWIM5wCmDvRgPdv5AKokAxaeHETGNu/GR5YTh6ig/Wk6csULJPTurlMYGwZo3WY8/S RfZp8I9Gy2yAoCI0+vjW2LTN6Od5sp32xYugCuM3yNL8mYeEFPoRNlT6vsQHGbg9He/V kmopjabwGeGIBJefSKtaXO7c6CDyrfAFN6OM+gnxLs8ESHOgBO5aCgV1hcMAY2jcPMfH T8fGBmkY7M50oGft9Gfh64w6tY1kmiqYy2+R4+MeC4Hi44IyXvvJ6AAeSPEY1x/MoGVc WPPg== X-Received: by 10.14.194.130 with SMTP id m2mr13743992een.96.1370015316743; Fri, 31 May 2013 08:48:36 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id s8sm67778346eeo.4.2013.05.31.08.48.34 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 May 2013 08:48:35 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 31 May 2013 17:48:29 +0200 Message-Id: <1370015309-4024-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQksU2KOe/jC2/2YhmhLsnAJwYsTVAvFoPZUWhCrCCDfQbTk+TKjX98rZvRmKULGAtDlugIx Cc: Takashi Iwai , Daniel Vetter , Paulo Zanoni Subject: [Intel-gfx] [PATCH] drm/i915: fix up the edp power well check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Now that we track the cpu transcoder we need accurately in the pipe config we can finally fix up the transcoder check. With the current code eDP on port D will be broken since we'd errornously cut the power. For reference see commit 2124b72e6283c4e84a55e71077fee91793f4c801 Author: Paulo Zanoni Date: Fri Mar 22 14:07:23 2013 -0300 drm/i915: don't disable the power well yet v2: - Kill the now outdated comment (Paulo) - Add the missing crtc->base.enabled check and consolidate it (Paulo) - Smash all checks together, looks neater that way. Cc: Takashi Iwai Cc: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3db4ed2..7cc953d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5801,20 +5801,11 @@ static void haswell_modeset_global_resources(struct drm_device *dev) struct intel_encoder *encoder; list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { - if (crtc->pipe != PIPE_A && crtc->base.enabled) - enable = true; - /* XXX: Should check for edp transcoder here, but thanks to init - * sequence that's not yet available. Just in case desktop eDP - * on PORT D is possible on haswell, too. */ - /* Even the eDP panel fitter is outside the always-on well. */ - if (crtc->config.pch_pfit.size && crtc->base.enabled) - enable = true; - } + if (!crtc->base.enabled) + continue; - list_for_each_entry(encoder, &dev->mode_config.encoder_list, - base.head) { - if (encoder->type != INTEL_OUTPUT_EDP && - encoder->connectors_active) + if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size || + crtc->config.cpu_transcoder != TRANSCODER_EDP) enable = true; }