From patchwork Sat Jun 1 15:17:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2648371 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 1AFA8DFE76 for ; Sat, 1 Jun 2013 15:20:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0C71E606C for ; Sat, 1 Jun 2013 08:20:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f45.google.com (mail-ee0-f45.google.com [74.125.83.45]) by gabe.freedesktop.org (Postfix) with ESMTP id 96539E6068 for ; Sat, 1 Jun 2013 08:17:22 -0700 (PDT) Received: by mail-ee0-f45.google.com with SMTP id l10so637167eei.18 for ; Sat, 01 Jun 2013 08:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=PS1lmaXj7OWR3OR4Lmm6jghjkaK5mSIIlgwl4RQj1hI=; b=aaBn81hWUs5EOLBBJm4cyCiqyAS/L0TG1Net1wPge8uFsKkJ5RSz/hS+Q3Yz9gIMEs Ewq2eyS3P/+V3ncNhjWDJ4ags4kOowFefWk/2tIcS4zh76VzWxHH3V9TGuIoUf2MBXgx 8F0/DsxQTkt9EV2tFHZgjHYtESHOMevHjRVOI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=PS1lmaXj7OWR3OR4Lmm6jghjkaK5mSIIlgwl4RQj1hI=; b=XD4AneOcRskWHNzLR/eYser9L4avXW8WKSy1eIf80fh5TO22oteQWqXX0Q5C5Q9bQQ RtNcRZMSqyCjbkUSIQuBuH9ORPbBgXGg8RlKun58A4ZNe1H9yaaqXMazxNGtwPcangEz EGGuz06BhGxspikD/tRhFSmJySbdrVgLajUl6uFZHdce0H4ySQqXAixMZ2cfASTALXX9 8aQEmRw6w90ufqwofvztVExpN/A1kmU+D2TxSeQ999Uy5ezvdHt6kGIhiEG0bdatAD0X 0Qa1ImfHrCacgdj9m1fhvVl55PWf7rftHhc/dWwuLaQL84aS63F1+TIi6ncT0CdAbSrC TUHw== X-Received: by 10.14.208.131 with SMTP id q3mr17062641eeo.111.1370099841804; Sat, 01 Jun 2013 08:17:21 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id h49sm41525445eew.7.2013.06.01.08.17.20 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 01 Jun 2013 08:17:21 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 1 Jun 2013 17:17:05 +0200 Message-Id: <1370099825-20461-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1370099825-20461-1-git-send-email-daniel.vetter@ffwll.ch> References: <1370099825-20461-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQnq7zFMDo3bnLoDrt6CxWinpkcgPqu+VO34m9bH++96EhczWQmnO0s4+UmO56OjOYBzLWrR Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/2] drm/i915: hw state readout support for pixel_multiplier X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Incomplete since ilk+ support needs proper pch dpll tracking first. SDVO get_config parts based on a patch from Jesse Barnes, but fixed up to actually work. Cc: Jesse Barnes Signed-off-by: Daniel Vetter Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_sdvo.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9f772eb..f126e18 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4965,6 +4965,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pfit_config(crtc, pipe_config); + if (INTEL_INFO(dev)->gen >= 4) { + tmp = I915_READ(DPLL_MD(crtc->pipe)); + pipe_config->pixel_multiplier = + ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) + >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; + } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { + tmp = I915_READ(DPLL(crtc->pipe)); + pipe_config->pixel_multiplier = + ((tmp & SDVO_MULTIPLIER_MASK) + >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; + } else { + /* Note that on i915G/GM the pixel multiplier is in the sdvo + * port and will be fixed up in the encoder->get_config + * function. */ + pipe_config->pixel_multiplier = 1; + } + return true; } @@ -5828,6 +5845,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, FDI_DP_PORT_WIDTH_SHIFT) + 1; ironlake_get_fdi_m_n_config(crtc, pipe_config); + + /* XXX: Can't properly read out the pch dpll pixel multiplier + * since we don't have state tracking for pch clocks yet. */ + pipe_config->pixel_multiplier = 1; + } else { + pipe_config->pixel_multiplier = 1; } intel_get_pipe_timings(crtc, pipe_config); @@ -5980,6 +6003,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && (I915_READ(IPS_CTL) & IPS_ENABLE); + pipe_config->pixel_multiplier = 1; + return true; } diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index f4588a2..5c816dd 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1313,9 +1313,13 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, static void intel_sdvo_get_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) { + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); struct intel_sdvo_dtd dtd; - u32 flags = 0; + int encoder_pixel_multiplier = 0; + u32 flags = 0, sdvox; + u8 val; bool ret; ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); @@ -1335,6 +1339,30 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, flags |= DRM_MODE_FLAG_NVSYNC; pipe_config->adjusted_mode.flags |= flags; + + if (IS_I915G(dev) || IS_I915GM(dev)) { + sdvox = I915_READ(intel_sdvo->sdvo_reg); + pipe_config->pixel_multiplier = + ((sdvox & SDVO_PORT_MULTIPLY_MASK) + >> SDVO_PORT_MULTIPLY_SHIFT) + 1; + } + + /* Cross check the port pixel multiplier with the sdvo encoder state. */ + intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1); + switch (val) { + case SDVO_CLOCK_RATE_MULT_1X: + encoder_pixel_multiplier = 1; + break; + case SDVO_CLOCK_RATE_MULT_2X: + encoder_pixel_multiplier = 2; + break; + case SDVO_CLOCK_RATE_MULT_4X: + encoder_pixel_multiplier = 4; + break; + } + WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, + "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", + pipe_config->pixel_multiplier, encoder_pixel_multiplier); } static void intel_disable_sdvo(struct intel_encoder *encoder)