From patchwork Sat Jun 1 21:53:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2649031 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 62592DFE76 for ; Sat, 1 Jun 2013 21:53:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1324AE5F81 for ; Sat, 1 Jun 2013 14:53:41 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by gabe.freedesktop.org (Postfix) with ESMTP id EBEA1E5EEA for ; Sat, 1 Jun 2013 14:53:30 -0700 (PDT) Received: by mail-ea0-f172.google.com with SMTP id g14so85560eak.31 for ; Sat, 01 Jun 2013 14:53:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=yG5k2d26aYeAkhed+I6fb24ULZ2SvFBjljWKBLQTyfM=; b=MWJmAzdhblWARSHVs7Qm8+Tn7s5jxKhpHUNqrnKUfYLVGXM93p94LPhAEpLGo93XSr QNswT53wwN63Wtrm31v2mE+GZ3Bl3TjZXLQNDX1XDEA8Nu0sodJI59sKDtCe7E6CRoe6 ilwoztJbYOnZQUTermu06T51H3YbIvU8XNpQA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=yG5k2d26aYeAkhed+I6fb24ULZ2SvFBjljWKBLQTyfM=; b=NJEw9N2LWUL7GzL7phE6IvPlNZjs8QmJ5qXWL5w/pVNrHTssfrP6bNwfDARzwbvEJr dMnUwtOuXoGmEzHVMRyWdrgAo8uxlE0A/Kjpj3dN/x5l7SGlgjCMqsegBW4hEHH3ayGl gvnzx0HORAMnTEyZrvb33Y7HyEj3lZxHAZKTgagZvrZqkTTS8Q2mL+RtX5MD2qdDVyLU hJlkXGUy6WIrgRY0Gd3mGGInOYXbnpqlXyTAzU1x5ShtxqstFCUqHTg7oUxf78HNe8y9 BDwTM3IQ06s8RKEJSy6RMLStnzB1KkqEOn2UEdIw/SYvOUWJWZZ3Y/ZTQZXf3wjoTY3C Akfg== X-Received: by 10.14.107.200 with SMTP id o48mr17737272eeg.35.1370123610090; Sat, 01 Jun 2013 14:53:30 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id w43sm45807431eel.0.2013.06.01.14.53.28 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 01 Jun 2013 14:53:28 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 1 Jun 2013 23:53:23 +0200 Message-Id: <1370123603-26750-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <20130601175239.GG11399@cantiga.alporthouse.com> References: <20130601175239.GG11399@cantiga.alporthouse.com> X-Gm-Message-State: ALoCoQk18O8RqsHVDfOVB1JTAwtOLmwwQwuKX7OSbNzE3Zke6FS2ZTSXuJTIPyoT31e+DTxZQtPG Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: fix EDID/sink-based bpp clamping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Since this is run in the compute config stage we need to check the new_ pointers, not the current modeset layout. Also there was a little logic bug in properly skipping connectors. This has been broken when moving the pipe bpp selection in commit 4e53c2e010e531b4a014692199e978482d471c7e Author: Daniel Vetter Date: Wed Mar 27 00:44:58 2013 +0100 drm/i915: precompute pipe bpp before touching the hw To avoid too much casting switch from drm_ to intel_ types. Also add a bit of debug output to help reconstructing what's going on. v2: Try to clarify this a bit: - s/pipe_config_set_bpp/compute_baseline_pipe_bpp/ to make it clearer at which stage this function is run. Also add a comment about what it does. - Extract the sink clamping into it's own function. v3: Actually make it compile. Cc: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 63 +++++++++++++++++++++++------------- 1 file changed, 41 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f410ede..d4b56cb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7567,13 +7567,39 @@ static void intel_modeset_commit_output_state(struct drm_device *dev) } } +static void +connected_sink_compute_bpp(struct intel_connector * connector, + struct intel_crtc_config *pipe_config) +{ + int bpp = pipe_config->pipe_bpp; + + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", + connector->base.base.id, + drm_get_connector_name(&connector->base)); + + /* Don't use an invalid EDID bpc value */ + if (connector->base.display_info.bpc && + connector->base.display_info.bpc * 3 < bpp) { + DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", + bpp, connector->base.display_info.bpc*3); + pipe_config->pipe_bpp = connector->base.display_info.bpc*3; + } + + /* Clamp bpp to 8 on screens without EDID 1.4 */ + if (connector->base.display_info.bpc == 0 && bpp > 24) { + DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", + bpp); + pipe_config->pipe_bpp = 24; + } +} + static int -pipe_config_set_bpp(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct intel_crtc_config *pipe_config) +compute_baseline_pipe_bpp(struct intel_crtc *crtc, + struct drm_framebuffer *fb, + struct intel_crtc_config *pipe_config) { - struct drm_device *dev = crtc->dev; - struct drm_connector *connector; + struct drm_device *dev = crtc->base.dev; + struct intel_connector *connector; int bpp; switch (fb->pixel_format) { @@ -7616,24 +7642,12 @@ pipe_config_set_bpp(struct drm_crtc *crtc, /* Clamp display bpp to EDID value */ list_for_each_entry(connector, &dev->mode_config.connector_list, - head) { - if (connector->encoder && connector->encoder->crtc != crtc) + base.head) { + if (!connector->new_encoder || + connector->new_encoder->new_crtc != crtc) continue; - /* Don't use an invalid EDID bpc value */ - if (connector->display_info.bpc && - connector->display_info.bpc * 3 < bpp) { - DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", - bpp, connector->display_info.bpc*3); - pipe_config->pipe_bpp = connector->display_info.bpc*3; - } - - /* Clamp bpp to 8 on screens without EDID 1.4 */ - if (connector->display_info.bpc == 0 && bpp > 24) { - DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", - bpp); - pipe_config->pipe_bpp = 24; - } + connected_sink_compute_bpp(connector, pipe_config); } return bpp; @@ -7714,7 +7728,12 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe; pipe_config->shared_dpll = DPLL_ID_PRIVATE; - plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config); + /* Compute a starting value for pipe_config->pipe_bpp taking the source + * plane pixel format and any sink constraints into account. Returns the + * source plane bpp so that dithering can be selected on mismatches + * after encoders and crtc also have had their say. */ + plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), + fb, pipe_config); if (plane_bpp < 0) goto fail;