From patchwork Mon Jun 3 18:41:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2654241 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 8AEFADF24C for ; Mon, 3 Jun 2013 18:42:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 48938E61B5 for ; Mon, 3 Jun 2013 11:42:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E8ADE5F2E for ; Mon, 3 Jun 2013 11:41:58 -0700 (PDT) Received: by mail-pb0-f50.google.com with SMTP id wy17so6073292pbc.9 for ; Mon, 03 Jun 2013 11:41:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=69wH0MrI9osPz4UMjydpICvhDSwce+nuE3NcvOJ523k=; b=K9q2iZdBojUtRmDA6KkZOVsKWttv3ZtjJbu91DIEh6JJdH5JRm+GfPMcgrCLFTblWy lRfTeanl0zDhGgLoccYNn/+rupwZD/Ak4heGeY2r2NJvP+AcBlnBhOnRcHwHey4oUnMO swC2lfY8VHLNPOmAckqvMpfviXD/D3YiHD64JnsGM8A/TX2Sk+TO/MuYPOpCOIIboBH2 SGYjdUs98nI2aBwE78lGFVkpYstojUF6obD1yTPUpW74TdAFs6NIKBa0fGWnGpOyjB9Y voL0gw9KEghIser4hJRAQGI6rzvuwPMU+y59+2D8W9U48sgRP8ujdEomzrtzn7Z32jZa 4LEg== X-Received: by 10.68.163.4 with SMTP id ye4mr24804118pbb.207.1370284918063; Mon, 03 Jun 2013 11:41:58 -0700 (PDT) Received: from localhost (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by mx.google.com with ESMTPSA id fm2sm64093883pab.13.2013.06.03.11.41.55 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 03 Jun 2013 11:41:57 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 3 Jun 2013 15:41:49 -0300 Message-Id: <1370284909-2106-1-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <20130603170340.GC5004@intel.com> References: <20130603170340.GC5004@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: WA: FBC Render Nuke. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org WaFbcNukeOn3DBlt for IVB, HSW. According BSPec: "Workaround: Do not enable Render Command Streamer tracking for FBC. Instead insert a LRI to address 0x50380 with data 0x00000004 after the PIPE_CONTROL that follows each render submission." v2: Chris noticed that flush_domains check was missing here and also suggested to do LRI only when fbc is enabled. To avoid do a I915_READ on every flush lets use the module parameter check. v3: Adding Wa name as Damien suggested. v4: Ville noticed VLV doesn't support fbc at all and comment came wrong from spec. v5: Ville noticed than on blt a Cache Clean LRI should be used instead the Nuke one. Cc: Ville Syrjälä Cc: Chris Wilson Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cc4c223..f37ddee 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -977,6 +977,9 @@ /* Framebuffer compression for Ivybridge */ #define IVB_FBC_RT_BASE 0x7020 +#define MSG_FBC_REND_STATE 0x50380 +#define FBC_REND_NUKE (1<<2) +#define FBC_REND_CACHE_CLEAN (1<<1) #define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 #define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1879188..e830a9b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -274,7 +274,7 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) struct drm_i915_gem_object *obj = intel_fb->obj; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); + I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset); if (!intel_edp_is_psr_enabled(dev)) I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3d2c236..3e24639 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -280,6 +280,30 @@ gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) return 0; } +static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, bool nuke) +{ + struct drm_device *dev = ring->dev; + int ret; + + if (i915_enable_fbc == 0) + return 0; + + if (i915_enable_fbc < 0 && !IS_HASWELL(dev)) + return 0; + + ret = intel_ring_begin(ring, 4); + if (ret) + return ret; + intel_ring_emit(ring, MI_NOOP); + /* WaFbcNukeOn3DBlt:ivb/hsw */ + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(ring, MSG_FBC_REND_STATE); + intel_ring_emit(ring, nuke ? FBC_REND_NUKE : FBC_REND_CACHE_CLEAN); + intel_ring_advance(ring); + + return 0; +} + static int gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, u32 flush_domains) @@ -336,6 +360,9 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, intel_ring_emit(ring, 0); intel_ring_advance(ring); + if (flush_domains) + return gen7_ring_fbc_flush(ring, true); + return 0; } @@ -1623,6 +1650,7 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, static int blt_ring_flush(struct intel_ring_buffer *ring, u32 invalidate, u32 flush) { + struct drm_device *dev = ring->dev; uint32_t cmd; int ret; @@ -1645,6 +1673,10 @@ static int blt_ring_flush(struct intel_ring_buffer *ring, intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); + + if (IS_GEN7(dev)) + return gen7_ring_fbc_flush(ring, false); + return 0; }