From patchwork Wed Jun 5 11:34:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2669131 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id B0C643FD4F for ; Wed, 5 Jun 2013 11:45:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9663DE6507 for ; Wed, 5 Jun 2013 04:45:26 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f180.google.com (mail-ea0-f180.google.com [209.85.215.180]) by gabe.freedesktop.org (Postfix) with ESMTP id AF673E64B9 for ; Wed, 5 Jun 2013 04:35:19 -0700 (PDT) Received: by mail-ea0-f180.google.com with SMTP id k10so1071250eaj.39 for ; Wed, 05 Jun 2013 04:35:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Lqwvtm/tvX1Ae+pBmDmuCehsve0NSTvMlWzH5d6PyEU=; b=IYNmhZtdhKeKbBgGujHChwTW3DtrE6m6O/TCxpS0R+UksYllpX11Ays06hPDcz16g2 g03x9zo3n+mfPrREz5Qac3NtHpKpl3SgXHloinqEHgYq2zTqXg6gf+hDznxIKT9eZtlx SBfWWRvri6YX/8mZ/xvwO9Y/Nn9GebdI1Jn/Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Lqwvtm/tvX1Ae+pBmDmuCehsve0NSTvMlWzH5d6PyEU=; b=aADIPDXDZaKTBbk/PxEpQ5FNmU45eYX3pbw27k+rdecRz7at4vyyWpmNy3WVKnUZ69 8qzVkPolcYG+VFD8Kn48/Q8miJEjAp2sA4Cv/J/aavHsSfLVQ0Jg86znrWZsV3ADc6Hh 66HGI3wY7DhCiZvbVX3ERzu0G36g+18rhJkZ71wZxuRzf0ipHVP6BZrxgR/xVNY1DIWP kbgQRgxOu2DuSKfca+jSH60PNGt7PqMD4avILEgaY4cMNhxWxPDxrAzpokWFpd7IQB9/ Tg8AqkdK9l/3mFohJJZbxjZA9YdHHfI1fiLLhnhzciuHsPF9ij4zmKDueuBRBYEQXspH stCA== X-Received: by 10.14.202.71 with SMTP id c47mr29253174eeo.87.1370432118967; Wed, 05 Jun 2013 04:35:18 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id bo9sm83152074eeb.9.2013.06.05.04.35.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 05 Jun 2013 04:35:18 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 5 Jun 2013 13:34:22 +0200 Message-Id: <1370432073-27634-21-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> References: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQlNHm3gaN/BCHIjA05g+ze9etWt2XUUEFg95jZESHf98/WG8x1Bh79XDdJ8m8PWNDFX7EbZ Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Just move the lowfreq_avail logic out of the register writing as a prep step for the next patch, which will coalesce all the pch pll enabling into one spot. Signed-off-by: Daniel Vetter Reviewed-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_display.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ecf0b1e..fc1b5f7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, if (encoder->pre_pll_enable) encoder->pre_pll_enable(encoder); - intel_crtc->lowfreq_avail = false; + if (is_lvds && has_reduced_clock && i915_powersave) + intel_crtc->lowfreq_avail = true; + else + intel_crtc->lowfreq_avail = false; if (intel_crtc->config.has_pch_encoder) { pll = intel_crtc_to_shared_dpll(intel_crtc); @@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, */ I915_WRITE(PCH_DPLL(pll->id), dpll); - if (is_lvds && has_reduced_clock && i915_powersave) { + if (has_reduced_clock) I915_WRITE(PCH_FP1(pll->id), fp2); - intel_crtc->lowfreq_avail = true; - } else { + else I915_WRITE(PCH_FP1(pll->id), fp); - } } intel_set_pipe_timings(intel_crtc);