From patchwork Wed Jun 5 11:34:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2668871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 20C29DF264 for ; Wed, 5 Jun 2013 11:36:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24F13E5CE0 for ; Wed, 5 Jun 2013 04:36:12 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f178.google.com (mail-ea0-f178.google.com [209.85.215.178]) by gabe.freedesktop.org (Postfix) with ESMTP id C218CE64D5 for ; Wed, 5 Jun 2013 04:34:52 -0700 (PDT) Received: by mail-ea0-f178.google.com with SMTP id q15so1076527ead.23 for ; Wed, 05 Jun 2013 04:34:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=cAT6MUHHzqmk0VByYIusHQadOJS0CexsBTLiif7AIwU=; b=Qox02d5Ykk5XLBqJEwPuougGMr7g8vhuVqX4OFW5tSYTCvA5vo0v6TL9livyz0SJR4 ScC9vNFQGwlzJq/wJtZUYGfL0/DVQfR4APAzkFEy4KS7aLQmkZdvqq+dvIglCLHGvjWt qlGt85UBZ84Kx5HFIW86kV+j+Xwm0Rl+efpZ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=cAT6MUHHzqmk0VByYIusHQadOJS0CexsBTLiif7AIwU=; b=E/jiTiUvFnGPY2DyB+4laBLaRk0z5VipI+YUyN9lVKPY2t5LsLZeiUI21OEtVVj3wm HztWvNm8/riKOt5iy+wMYpTBTZIdAtD60Gf12YUTqZ4GEBWTgzS0ZPiEIbdwZ0cDH3fP SEl9r7g4WFVB8YEwt6SOYvtUKMFvvcVMueAFDvd1+H5wjbkvAI98jPbd/IwLr6NoiJYp l8DiGfuXmWqI7bwNLRpFtjcsgP8OQnLoaV1O+5aLXN1EoNmf+/Wt7ALQikUTPvx4tP2p 23DNT8a8XsmPaMmXJnbS+16LvO+6p8f6yQX9sWNKj0pCkX5cngSiP+BT8256rod2uQJV ++gw== X-Received: by 10.14.39.71 with SMTP id c47mr1385395eeb.141.1370432091822; Wed, 05 Jun 2013 04:34:51 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id bo9sm83152074eeb.9.2013.06.05.04.34.43 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 05 Jun 2013 04:34:50 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 5 Jun 2013 13:34:04 +0200 Message-Id: <1370432073-27634-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> References: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkggYm9gIwhBqtKSeW1UIAKICJnlKyInsOFkU2AKjmcyYqWU3klggwYzynZ0J5mGqnXP9sL Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 02/31] drm/i915: conditionally disable pch resources in ilk_crtc_disable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Simlar to how disable already works on haswell. This is possible since we now carefully track the pch state in the pipe config. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 69 +++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3bdb695..56fb6ed 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3380,7 +3380,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) if (dev_priv->cfb_plane == plane) intel_disable_fbc(dev); - intel_set_pch_fifo_underrun_reporting(dev, pipe, false); + if (intel_crtc->config.has_pch_encoder) + intel_set_pch_fifo_underrun_reporting(dev, pipe, false); + intel_disable_pipe(dev_priv, pipe); ironlake_pfit_disable(intel_crtc); @@ -3389,42 +3391,45 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) if (encoder->post_disable) encoder->post_disable(encoder); - ironlake_fdi_disable(crtc); + if (intel_crtc->config.has_pch_encoder) { + ironlake_fdi_disable(crtc); - ironlake_disable_pch_transcoder(dev_priv, pipe); - intel_set_pch_fifo_underrun_reporting(dev, pipe, true); + ironlake_disable_pch_transcoder(dev_priv, pipe); + intel_set_pch_fifo_underrun_reporting(dev, pipe, true); - if (HAS_PCH_CPT(dev)) { - /* disable TRANS_DP_CTL */ - reg = TRANS_DP_CTL(pipe); - temp = I915_READ(reg); - temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); - temp |= TRANS_DP_PORT_SEL_NONE; - I915_WRITE(reg, temp); - - /* disable DPLL_SEL */ - temp = I915_READ(PCH_DPLL_SEL); - switch (pipe) { - case 0: - temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); - break; - case 1: - temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); - break; - case 2: - /* C shares PLL A or B */ - temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); - break; - default: - BUG(); /* wtf */ + if (HAS_PCH_CPT(dev)) { + /* disable TRANS_DP_CTL */ + reg = TRANS_DP_CTL(pipe); + temp = I915_READ(reg); + temp &= ~(TRANS_DP_OUTPUT_ENABLE | + TRANS_DP_PORT_SEL_MASK); + temp |= TRANS_DP_PORT_SEL_NONE; + I915_WRITE(reg, temp); + + /* disable DPLL_SEL */ + temp = I915_READ(PCH_DPLL_SEL); + switch (pipe) { + case 0: + temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); + break; + case 1: + temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); + break; + case 2: + /* C shares PLL A or B */ + temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); + break; + default: + BUG(); /* wtf */ + } + I915_WRITE(PCH_DPLL_SEL, temp); } - I915_WRITE(PCH_DPLL_SEL, temp); - } - /* disable PCH DPLL */ - intel_disable_pch_pll(intel_crtc); + /* disable PCH DPLL */ + intel_disable_pch_pll(intel_crtc); - ironlake_fdi_pll_disable(intel_crtc); + ironlake_fdi_pll_disable(intel_crtc); + } intel_crtc->active = false; intel_update_watermarks(dev);