From patchwork Wed Jun 5 11:34:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2668931 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id E27ABDF264 for ; Wed, 5 Jun 2013 11:38:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B1268E64D0 for ; Wed, 5 Jun 2013 04:38:53 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B8C8E64B9 for ; Wed, 5 Jun 2013 04:35:00 -0700 (PDT) Received: by mail-ea0-f172.google.com with SMTP id l15so676400eak.3 for ; Wed, 05 Jun 2013 04:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=YcwcgIiz/WHjsGsuQ0362tuKT7uNjgp2cBqDDJeFIQ0=; b=J/91KYTySoqpF/Y97M4bRimkxDTIimFSKO46ZJ5NRnRZON4lIBgJJhOFPpmes2ShoT 2UfH3ntLYklYhoGa+spZ2No1bmrMKfUtCKdT2UE1zeh8n2SvXcfAYJOvCXa3Aub8sC/4 CeqmaKgAlXGyQ5vR3euc4kyiD9y95DIhG6WMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=YcwcgIiz/WHjsGsuQ0362tuKT7uNjgp2cBqDDJeFIQ0=; b=nDYVNLHGChEWA9IuJpkwrHKcoF1XPDCXMDMvIuj/A75Gklc8qTJitrkyhiPpn0LRhB zBmJJySy1MsAL5p1hlFTVOtuwwnR8jNChYLHfxBWiMh9ftUcEWTnkbUncMZ+Nr0IRphP 0foCMaQZdgjFRdy4HfhZ1QfYB7c97mRz1d3Lt3L2lIST0InPFiCRlRk7Lj9iKoMl89OT 0KUwRA7ZWLIK2UZ9rPWqaldf+4WgYoaWWD2/qbk8AIbudtmpW86Cl4X864XeXJVbXjvc PMHuuNjo3ErOLY6ExbELVMdvBmYQ6Zf/vnuTTe2M6grufzPpwoTZMCQ+aP+61u8mqMQb /BZg== X-Received: by 10.15.82.193 with SMTP id a41mr19285651eez.39.1370432099681; Wed, 05 Jun 2013 04:34:59 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id bo9sm83152074eeb.9.2013.06.05.04.34.57 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 05 Jun 2013 04:34:58 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 5 Jun 2013 13:34:09 +0200 Message-Id: <1370432073-27634-8-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> References: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkpUni/CvCfWvVOWq07618kI7hEPnn14J/N/0SHfKcvOPZsZLOOZcZf0oSgL+JMvYPrsMLs Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 07/31] drm/i915: refactor PCH_DPLL_SEL #defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The bits are evenly space, so we can cut down on two big switch blocks. This also greatly simplifies the hw state readout which follows in the next patch. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 12 +++--------- drivers/gpu/drm/i915/intel_display.c | 32 +++----------------------------- 2 files changed, 6 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 47a9de0..68ea707 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3980,15 +3980,9 @@ #define PCH_SSC4_AUX_PARMS 0xc6214 #define PCH_DPLL_SEL 0xc7000 -#define TRANSA_DPLL_ENABLE (1<<3) -#define TRANSA_DPLLB_SEL (1<<0) -#define TRANSA_DPLLA_SEL 0 -#define TRANSB_DPLL_ENABLE (1<<7) -#define TRANSB_DPLLB_SEL (1<<4) -#define TRANSB_DPLLA_SEL (0) -#define TRANSC_DPLL_ENABLE (1<<11) -#define TRANSC_DPLLB_SEL (1<<8) -#define TRANSC_DPLLA_SEL (0) +#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) +#define TRANS_DPLLA_SEL(pipe) 0 +#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) /* transcoder */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b09c9a2..a44c43c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2952,21 +2952,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) u32 sel; temp = I915_READ(PCH_DPLL_SEL); - switch (pipe) { - default: - case 0: - temp |= TRANSA_DPLL_ENABLE; - sel = TRANSA_DPLLB_SEL; - break; - case 1: - temp |= TRANSB_DPLL_ENABLE; - sel = TRANSB_DPLLB_SEL; - break; - case 2: - temp |= TRANSC_DPLL_ENABLE; - sel = TRANSC_DPLLB_SEL; - break; - } + temp |= TRANS_DPLL_ENABLE(pipe); + sel = TRANS_DPLLB_SEL(pipe); if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) temp |= sel; else @@ -3425,20 +3412,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) /* disable DPLL_SEL */ temp = I915_READ(PCH_DPLL_SEL); - switch (pipe) { - case 0: - temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); - break; - case 1: - temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); - break; - case 2: - /* C shares PLL A or B */ - temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); - break; - default: - BUG(); /* wtf */ - } + temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); I915_WRITE(PCH_DPLL_SEL, temp); }