From patchwork Thu Jun 6 08:22:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2678111 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 44187DF23A for ; Thu, 6 Jun 2013 08:24:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5397CE6637 for ; Thu, 6 Jun 2013 01:24:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by gabe.freedesktop.org (Postfix) with ESMTP id D4D5AE661C for ; Thu, 6 Jun 2013 01:23:00 -0700 (PDT) Received: by mail-ea0-f172.google.com with SMTP id q10so1000716eaj.17 for ; Thu, 06 Jun 2013 01:23:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=MTLwl5Y1EuFRcT8Mme9EeGiXyD1e/WLZnn/6Bck4Js4=; b=I1ZJexsXxxFNvybmuwY63YC9tiuvCddIpRZ39Tyy8GAEJ60rQn32pIKHgRvx+YUfL9 czq7XtXgEOlZLjDCX1/odIEdAC6DD9SqXuiBuQAiGG6/4MeQ+xvwQkceAL+cakhkbQ6b rP9fQ3BMAHGL4WW/MOBbTysEDSfPpV4pmWRq0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=MTLwl5Y1EuFRcT8Mme9EeGiXyD1e/WLZnn/6Bck4Js4=; b=Jk0aB9BExHOeL4f1Fha72nVHJJXiQFTzxMGwOVWG+nJymqHoRFCWcbjEJtw/dS4jQg xAcEAftxAtF0tD+/uCSTBUICTjpMsJeBrR991+L4Pqh5bOYn7e+g1EsjBGuoPLJ/x1a2 a4UGTaxRZPgYkNNMfhvmr/wbcYV0aRfwipgHsz+WjTmQOv2MWZ7l+41rcarz/mTQCYPU EXnygw+9kUvjmUF0syeUFLbAO6BwdIzDqCMB5oQXNWiHSmSi0LVnHK9e+Vgugj7811nI 0bj1f9N8h32K3TAsSy80QB3OBCn4tbr1eWGe0WvIEc4RqmIEbjUrUAczXQPtywBILJZC Z3lA== X-Received: by 10.14.178.6 with SMTP id e6mr8463705eem.64.1370506979885; Thu, 06 Jun 2013 01:22:59 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id p43sm61802140eem.11.2013.06.06.01.22.58 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 06 Jun 2013 01:22:58 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 6 Jun 2013 10:22:53 +0200 Message-Id: <1370506973-11989-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1370432073-27634-30-git-send-email-daniel.vetter@ffwll.ch> References: <1370432073-27634-30-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQksHr2yhvxNxXZiOtm+ot9wVLPyOIYQHcINuAXQK/utNANvDIwr/zUxz5b/Fzqc3ftUVFZK Cc: Jani Nikula , Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org No need to call the ->pre_pll_enable hook twice if we don't enable the dpll too early. This should make Jani a bit less grumpy. v2: Rebase on top of the newly-colored BUG_ONs. Cc: Jani Nikula Signed-off-by: Daniel Vetter Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++--------------------- 1 file changed, 18 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5e43b9a..6e4d666 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1268,32 +1268,38 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); } -static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) +static void vlv_enable_pll(struct intel_crtc *crtc) { - int reg; - u32 val; + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int reg = DPLL(crtc->pipe); + u32 dpll = crtc->config.dpll_hw_state.dpll; - assert_pipe_disabled(dev_priv, pipe); + assert_pipe_disabled(dev_priv, crtc->pipe); /* No really, not for ILK+ */ BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); /* PLL is protected by panel, make sure we can write it */ if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) - assert_panel_unlocked(dev_priv, pipe); + assert_panel_unlocked(dev_priv, crtc->pipe); + + I915_WRITE(reg, dpll); + POSTING_READ(reg); + udelay(150); + + if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) + DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); - reg = DPLL(pipe); - val = I915_READ(reg); - val |= DPLL_VCO_ENABLE; /* We do this three times for luck */ - I915_WRITE(reg, val); + I915_WRITE(reg, dpll); POSTING_READ(reg); udelay(150); /* wait for warmup */ - I915_WRITE(reg, val); + I915_WRITE(reg, dpll); POSTING_READ(reg); udelay(150); /* wait for warmup */ - I915_WRITE(reg, val); + I915_WRITE(reg, dpll); POSTING_READ(reg); udelay(150); /* wait for warmup */ } @@ -3561,7 +3567,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) if (encoder->pre_pll_enable) encoder->pre_pll_enable(encoder); - vlv_enable_pll(dev_priv, pipe); + vlv_enable_pll(intel_crtc); for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->pre_enable) @@ -4315,7 +4321,6 @@ static void vlv_update_pll(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_encoder *encoder; int pipe = crtc->pipe; u32 dpll, mdiv; u32 bestn, bestm1, bestm2, bestp1, bestp2; @@ -4403,10 +4408,6 @@ static void vlv_update_pll(struct intel_crtc *crtc) vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); - for_each_encoder_on_crtc(dev, &crtc->base, encoder) - if (encoder->pre_pll_enable) - encoder->pre_pll_enable(encoder); - /* Enable DPIO clock input */ dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; @@ -4416,20 +4417,10 @@ static void vlv_update_pll(struct intel_crtc *crtc) dpll |= DPLL_VCO_ENABLE; crtc->config.dpll_hw_state.dpll = dpll; - I915_WRITE(DPLL(pipe), dpll); - POSTING_READ(DPLL(pipe)); - udelay(150); - - if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) - DRM_ERROR("DPLL %d failed to lock\n", pipe); - dpll_md = (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; crtc->config.dpll_hw_state.dpll_md = dpll_md; - I915_WRITE(DPLL_MD(pipe), dpll_md); - POSTING_READ(DPLL_MD(pipe)); - if (crtc->config.has_dp_encoder) intel_dp_set_m_n(crtc);