From patchwork Fri Jun 7 21:10:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2690071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id B37A540077 for ; Fri, 7 Jun 2013 21:11:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8CA0E68BE for ; Fri, 7 Jun 2013 14:11:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f174.google.com (mail-ea0-f174.google.com [209.85.215.174]) by gabe.freedesktop.org (Postfix) with ESMTP id C8A39E68AA for ; Fri, 7 Jun 2013 14:10:39 -0700 (PDT) Received: by mail-ea0-f174.google.com with SMTP id o10so752924eaj.19 for ; Fri, 07 Jun 2013 14:10:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=DaQAIaAhbilZDPXNDR5xTK5FyJGkqH5J2cg9oFOGD+o=; b=HkbuVv7cLrVwrIHGISWP1xOhLPwguQ7cx07EzrGxXwjVsgQ3c4XzG/xNxYHmTgPCJo n7UezkPH/IF6GwvAyYsF1WaRuHtpw6eAVRVNpfmaxhn6YxYeCvv5dq4dINrupmbP8yM5 jT4HkW0joQINQE5nao+U2XQCo9gZA43sgsQUU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=DaQAIaAhbilZDPXNDR5xTK5FyJGkqH5J2cg9oFOGD+o=; b=MGMiWPmMSxuOYs3ivErOlGyNVJZOBDDFOxtbeikAv8yfjuFKupSxURwkqB3lc8V4zl Fzh1RXxsWIfkfLQ9WD0pOoeU0f674sUABvl7gHW+9TUWoi1L2awpOsMyFLB+d1Ffkbxk gUo4ZjeRUsaRwVDoOhx+T7zK8RcWvb0e52jWyG0R8Yi6LuvBx47deEYFmdaZz7kC9+xd 4CB190Y6mTCZfbplGwNbupTRCHsakCjv3ZyKk2bAl7qKhtNTDsPLypxZ/W6NO6Lt/26q QP0ZFtaBZN5ECMDs0FBb6FrcZfahC8tGqO9DW64kDIa04PrQ9enbyToAxygg83KZg9bS xTGg== X-Received: by 10.14.216.201 with SMTP id g49mr503688eep.42.1370639438947; Fri, 07 Jun 2013 14:10:38 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id cf47sm864012eeb.17.2013.06.07.14.10.37 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 07 Jun 2013 14:10:38 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 7 Jun 2013 23:10:32 +0200 Message-Id: <1370639432-1229-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <20130607170316.GT5004@intel.com> References: <20130607170316.GT5004@intel.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmQgZq80MKNXb3Pkvp1T5dyuWc6CsYa2lSBB3jrYt9ZFmwwhRaq5Q/bLCOLft2lpcbIPKBU Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: move shared_dpll into the pipe config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org With the big sed-job prep work done this is now really simple. With the exception that we only assign the right shared dpll id in the ->mode_set callback but also depend upon the old one still being around. Until that mess is fixed up we need to jump through a few hoops to keep the old value save. v2: Kill the funny whitespace spotted by Chris. v3: Move the shared_dpll pipe config fixup into this patch as noticed by Ville. Also unconditionally set the shared_dpll with the current one, since otherwise we won't handle direct pch port -> cpu edp transitions correctly. Cc: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++----------- drivers/gpu/drm/i915/intel_drv.h | 5 +++-- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3926a80..69240f7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -896,10 +896,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; - if (crtc->shared_dpll < 0) + if (crtc->config.shared_dpll < 0) return NULL; - return &dev_priv->shared_dplls[crtc->shared_dpll]; + return &dev_priv->shared_dplls[crtc->config.shared_dpll]; } /* For ILK+ */ @@ -2982,7 +2982,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) sel = TRANSC_DPLLB_SEL; break; } - if (intel_crtc->shared_dpll == DPLL_ID_PCH_PLL_B) + if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) temp |= sel; else temp &= ~sel; @@ -3068,7 +3068,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc) WARN_ON(pll->active); } - crtc->shared_dpll = DPLL_ID_PRIVATE; + crtc->config.shared_dpll = DPLL_ID_PRIVATE; } static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp) @@ -3124,7 +3124,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, return NULL; found: - crtc->shared_dpll = i; + crtc->config.shared_dpll = i; DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe)); if (pll->active == 0) { DRM_DEBUG_DRIVER("setting up pll %d\n", i); @@ -4087,12 +4087,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc, pipe_config->pipe_bpp == 24; } -static int intel_crtc_compute_config(struct drm_crtc *crtc, +static int intel_crtc_compute_config(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config) { - struct drm_device *dev = crtc->dev; + struct drm_device *dev = crtc->base.dev; struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); if (HAS_PCH_SPLIT(dev)) { /* FDI link clock is fixed at 2.7G */ @@ -4123,10 +4122,15 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc, } if (IS_HASWELL(dev)) - hsw_compute_ips_config(intel_crtc, pipe_config); + hsw_compute_ips_config(crtc, pipe_config); + + /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old + * clock survives for now. */ + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) + pipe_config->shared_dpll = crtc->config.shared_dpll; if (pipe_config->has_pch_encoder) - return ironlake_fdi_compute_config(intel_crtc, pipe_config); + return ironlake_fdi_compute_config(crtc, pipe_config); return 0; } @@ -7891,7 +7895,7 @@ encoder_retry: if (!pipe_config->port_clock) pipe_config->port_clock = pipe_config->adjusted_mode.clock; - ret = intel_crtc_compute_config(crtc, pipe_config); + ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); if (ret < 0) { DRM_DEBUG_KMS("CRTC fixup failed\n"); goto fail; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1d4ec20..b77df04 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -252,6 +252,9 @@ struct intel_crtc_config { * haswell. */ struct dpll dpll; + /* Selected dpll when shared or DPLL_ID_PRIVATE. */ + enum intel_dpll_id shared_dpll; + int pipe_bpp; struct intel_link_m_n dp_m_n; @@ -316,8 +319,6 @@ struct intel_crtc { struct intel_crtc_config config; - /* We can share PLLs across outputs if the timings match */ - enum intel_dpll_id shared_dpll; uint32_t ddi_pll_sel; /* reset counter value when the last flip was submitted */