From patchwork Wed Jun 12 11:37:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2709581 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 767DE9F4BB for ; Wed, 12 Jun 2013 11:45:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5BBF420248 for ; Wed, 12 Jun 2013 11:45:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2B1C120188 for ; Wed, 12 Jun 2013 11:45:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04331E6366 for ; Wed, 12 Jun 2013 04:45:42 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by gabe.freedesktop.org (Postfix) with ESMTP id E9E16E604B for ; Wed, 12 Jun 2013 04:38:38 -0700 (PDT) Received: by mail-ea0-f172.google.com with SMTP id q10so5552504eaj.31 for ; Wed, 12 Jun 2013 04:38:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=IZAYBoNSch6mkStZ5hsjM+jL9YefLwSMh/+Qs2oZX6g=; b=ZLfNkN5lmoVtqL+X8WhjAZl63o2wM9ivyT59Lme3GfruUIcrrsleqvdaw//+3/HaMv ypdzEwTnPf0bzpK+hRcmSXGyMcOIkMTl31PTD5yPBfe9tUTJujsAh6zafUZCZVTiImVj z9ZJ6ZIwUIepaeNIzmtM/l/fo8CqTr5qADfoc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=IZAYBoNSch6mkStZ5hsjM+jL9YefLwSMh/+Qs2oZX6g=; b=DFNY+kE8Rh1nxLBcnKVTqW/OVoZV2SdN3kBPNUbcBoX/yC65P8LHZv/1VwhN6jBmxH vwtiytWwMKZ3mvLxqh3YaHIFWVvu6URE0scVMSY7UU4ByPQHuJ2poQDCzJlk2Y6P/TX0 JgFV2iLY3LENQocMYFjmuqN2tRgNQ1PSIrWfuiJrB2Xqy76y7j5J/7/7hwtnEke1Bkfb 0jVq0AYGbEfq4ZWMXuPagXLgp3kxZNmWbBk7zePGSWhRQDI2Xx5ja8jj8H7eO46ucPa3 bjmxaC9Tj4ZDq60nZdtboIn/oi6h7MF2Y7MfAQwTa70lfa6w+oK8A17RPP32+6XIPMhz DdiA== X-Received: by 10.15.94.11 with SMTP id ba11mr1374805eeb.101.1371037118213; Wed, 12 Jun 2013 04:38:38 -0700 (PDT) Received: from natalie.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id 3sm36309753een.7.2013.06.12.04.38.36 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 12 Jun 2013 04:38:37 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 12 Jun 2013 13:37:15 +0200 Message-Id: <1371037046-3732-14-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1371037046-3732-1-git-send-email-daniel.vetter@ffwll.ch> References: <1371037046-3732-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmYa5yRTH5WMUOwwrooWkoIO6JHgnkWtfAXfdty5JIpjj/oKn0vxMK6IyJxEafpRRkSf7Xc Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 13/24] drm/i915: kill lpt pch transcoder->crtc mapping code for fifo underruns X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It's racy: There's no guarantee that we won't walk this code (due to a pch fifo underrun interrupt) while someone is changing the pointers around. The only reason we do this is to use the righ crtc for the pch fifo underrun accounting. But we never expose this to userspace, so essentially no one really cares if we use the "wrong" crtc. So let's just rip it out. With this patch fifo underrun code will always use crtc A for tracking underruns on the (only) pch transcoder on LPT. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 33 +++++++-------------------------- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index bb26555..b98ea4e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -193,13 +193,13 @@ static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, POSTING_READ(SDEIMR); } -static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc, +static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, + enum transcoder pch_transcoder, bool enable) { - struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER : - SDE_TRANSB_FIFO_UNDER; + uint32_t bit = (pch_transcoder == TRANSCODER_A) ? + SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; ibx_display_interrupt_update(dev_priv, bit, enable ? bit : 0); @@ -292,30 +292,11 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, bool enable) { struct drm_i915_private *dev_priv = dev->dev_private; - enum pipe p; - struct drm_crtc *crtc; - struct intel_crtc *intel_crtc; + struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); unsigned long flags; bool ret; - if (HAS_PCH_LPT(dev)) { - crtc = NULL; - for_each_pipe(p) { - struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p]; - if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) { - crtc = c; - break; - } - } - if (!crtc) { - DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n"); - return false; - } - } else { - crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; - } - intel_crtc = to_intel_crtc(crtc); - spin_lock_irqsave(&dev_priv->irq_lock, flags); ret = !intel_crtc->pch_fifo_underrun_disabled; @@ -326,7 +307,7 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, intel_crtc->pch_fifo_underrun_disabled = !enable; if (HAS_PCH_IBX(dev)) - ibx_set_fifo_underrun_reporting(intel_crtc, enable); + ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); else cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);