| Message ID | 1371064278-11859-1-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 12 Jun 2013 22:11:18 +0300 ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The specs are a bit unclear whether the per-plane trickle feed disable > control exists on VLV. There is another trickle feed disable control > in the MI_ARB register. > > After some experimentation it turns out both the DSPCNTR trickle feed > bits and the MI_ARB bit can be toggled. However the DSPCNTR bits don't > seem to have any effect. > > The MI_ARB bit, on the other hand, has a noticable effect. I performed > an experiment where I reduced the FIFO size via DSPARB and observed the > effect of the MI_ARB trickle feed bit on the display. > > Using a 1920x1080-60 mode, with MI_ARB=0x4 the display started to have > problems with DSPARB=0x42424242, whereas with MI_ARB=0x0 the problems > didn't start until DSPARB=0x09090909. This seems to confirm that the > MI_ARB trickle feed bit actually does work. > > So replace the use of the DSPCNTR trickle feed bits with MI_ARB > on VLV. > > v2: Amend commit message with results from experimentation > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index cd37ca4..9cb6236 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1372,6 +1372,8 @@ > #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) > #define FW_CSPWRDWNEN (1<<15) > > +#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) > + > /* > * Palette regs > */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index adc44e4..b27bda0 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4873,7 +4873,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > > I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > > - g4x_disable_trickle_feed(dev); > + I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > > I915_WRITE(CACHE_MODE_1, > _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); Seems ok, though it would be nice to get some power numbers for it. Is this a win, lose, or wash wrt power? Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
On Wed, Jun 12, 2013 at 02:19:38PM -0700, Jesse Barnes wrote: > On Wed, 12 Jun 2013 22:11:18 +0300 > ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > The specs are a bit unclear whether the per-plane trickle feed disable > > control exists on VLV. There is another trickle feed disable control > > in the MI_ARB register. > > > > After some experimentation it turns out both the DSPCNTR trickle feed > > bits and the MI_ARB bit can be toggled. However the DSPCNTR bits don't > > seem to have any effect. > > > > The MI_ARB bit, on the other hand, has a noticable effect. I performed > > an experiment where I reduced the FIFO size via DSPARB and observed the > > effect of the MI_ARB trickle feed bit on the display. > > > > Using a 1920x1080-60 mode, with MI_ARB=0x4 the display started to have > > problems with DSPARB=0x42424242, whereas with MI_ARB=0x0 the problems > > didn't start until DSPARB=0x09090909. This seems to confirm that the > > MI_ARB trickle feed bit actually does work. > > > > So replace the use of the DSPCNTR trickle feed bits with MI_ARB > > on VLV. > > > > v2: Amend commit message with results from experimentation > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > drivers/gpu/drm/i915/intel_pm.c | 2 +- > > 2 files changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index cd37ca4..9cb6236 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1372,6 +1372,8 @@ > > #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) > > #define FW_CSPWRDWNEN (1<<15) > > > > +#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) > > + > > /* > > * Palette regs > > */ > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index adc44e4..b27bda0 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4873,7 +4873,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > > > > I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > > > > - g4x_disable_trickle_feed(dev); > > + I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > > > > I915_WRITE(CACHE_MODE_1, > > _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > > Seems ok, though it would be nice to get some power numbers for it. Is > this a win, lose, or wash wrt power? > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cd37ca4..9cb6236 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1372,6 +1372,8 @@ #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) #define FW_CSPWRDWNEN (1<<15) +#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) + /* * Palette regs */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index adc44e4..b27bda0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4873,7 +4873,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); - g4x_disable_trickle_feed(dev); + I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));