| Message ID | 1371070554-1947-1-git-send-email-rodrigo.vivi@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2013/6/12 Rodrigo Vivi <rodrigo.vivi@gmail.com>: > From: Shobhit Kumar <shobhit.kumar@intel.com> > > v2: Modified and corrected the structures to be more in line for > kernel coding guidelines and rebased the code on Paulo's DP patchset > v3: removing unecessary identation at DP_RECEIVER_CAP_SIZE > v4: moving them to include/drm/drm_dp_helper.h and also already > icluding EDP_PSR_RECEIVER_CAP_SIZE to add everything needed > for PSR at once at drm_dp_helper.h > v5: Fix SDP VSC header and identation by (Paulo Zanoni) and > remove i915 from title (Daniel Vetter) > > CC: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com> > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> > --- > include/drm/drm_dp_helper.h | 33 ++++++++++++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e8e1417..4062c9e 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -342,13 +342,44 @@ u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], > u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], > int lane); > > -#define DP_RECEIVER_CAP_SIZE 0xf > +#define DP_RECEIVER_CAP_SIZE 0xf > +#define EDP_PSR_RECEIVER_CAP_SIZE 2 > + > void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); > > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); > > +/* SDP header as per eDP 1.3 spec, section 3.6 */ On my version of the spec, it's section 3.5, same for the comment below. Maybe we should just include the chapter name ("PSR Secondary Data Packet Support") or just don't add anything. These numbers might change in the future. Everything else looks correct, so with or without the comment fixed: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > +struct edp_sdp_header { > + u8 HB0; /* Secondary Data Packet ID */ > + u8 HB1; /* Secondary Data Packet Type */ > + u8 HB2; /* 7:5 reserved, 4:0 revision number */ > + u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ > +} __packed; > + > +#define EDP_SDP_HEADER_REVISION_MASK 0x1F > +#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F > + > +/* SDP VSC header as per eDP 1.3 spec, section 3.6 */ > +struct edp_vsc_psr { > + struct edp_sdp_header sdp_header; > + u8 DB0; /* Stereo Interface */ > + u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ > + u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ > + u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ > + u8 DB4; /* CRC value bits 7:0 of the G or Y component */ > + u8 DB5; /* CRC value bits 15:8 of the G or Y component */ > + u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ > + u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ > + u8 DB8_31[24]; /* Reserved */ > +} __packed; > + > +#define EDP_VSC_PSR_STATE_ACTIVE (1<<0) > +#define EDP_VSC_PSR_UPDATE_RFB (1<<1) > +#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) > + > static inline int > drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > -- > 1.7.11.7 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e8e1417..4062c9e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -342,13 +342,44 @@ u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], int lane); -#define DP_RECEIVER_CAP_SIZE 0xf +#define DP_RECEIVER_CAP_SIZE 0xf +#define EDP_PSR_RECEIVER_CAP_SIZE 2 + void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); u8 drm_dp_link_rate_to_bw_code(int link_rate); int drm_dp_bw_code_to_link_rate(u8 link_bw); +/* SDP header as per eDP 1.3 spec, section 3.6 */ +struct edp_sdp_header { + u8 HB0; /* Secondary Data Packet ID */ + u8 HB1; /* Secondary Data Packet Type */ + u8 HB2; /* 7:5 reserved, 4:0 revision number */ + u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ +} __packed; + +#define EDP_SDP_HEADER_REVISION_MASK 0x1F +#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F + +/* SDP VSC header as per eDP 1.3 spec, section 3.6 */ +struct edp_vsc_psr { + struct edp_sdp_header sdp_header; + u8 DB0; /* Stereo Interface */ + u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ + u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ + u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ + u8 DB4; /* CRC value bits 7:0 of the G or Y component */ + u8 DB5; /* CRC value bits 15:8 of the G or Y component */ + u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ + u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ + u8 DB8_31[24]; /* Reserved */ +} __packed; + +#define EDP_VSC_PSR_STATE_ACTIVE (1<<0) +#define EDP_VSC_PSR_UPDATE_RFB (1<<1) +#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) + static inline int drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {