From patchwork Wed Jun 12 22:54:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2712731 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 36C189F4BB for ; Wed, 12 Jun 2013 22:56:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5CBE0201FC for ; Wed, 12 Jun 2013 22:56:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7E6FA201F2 for ; Wed, 12 Jun 2013 22:56:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90B83E6465 for ; Wed, 12 Jun 2013 15:56:09 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f174.google.com (mail-ea0-f174.google.com [209.85.215.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 4983AE5C53 for ; Wed, 12 Jun 2013 15:55:10 -0700 (PDT) Received: by mail-ea0-f174.google.com with SMTP id o10so4162753eaj.5 for ; Wed, 12 Jun 2013 15:55:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Jtkrt+hlFuMopjN+AH7/xAmGlZ5hRk8iD4ePc6RMtfY=; b=h3CiV0TgSnrYLRs0bGnMeKhdsoWZvt4Tnjn78gDYYxO+4YBpg5o66upmiWTkWCs1tN rf+QCtybIvZbfQDbBT0UlOp2dZPyavTuT/IaMReQ5Z/BUcjEeRma/3L07sE9BRJEKMJF nud/F58Tg8KHg0+nxs1n15w0BdP4Hyr8/1bFY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Jtkrt+hlFuMopjN+AH7/xAmGlZ5hRk8iD4ePc6RMtfY=; b=SIEYboN8zyKf0LA83tNlk1i/JNmnNRdAOVlaaQYMA2GsBrFAf/qkAJWuhioh5Y9Wpn RU0dFcM5O9vwoVHUn0w7+jXDbD+sOaMRZWdRivqmxrcPiuS5UypYDlMBs9o2Nd8YT/JS 49iq+95wstLPuaNb478ySQHT8OEwLC36JRYeXSG/FVe/zczFrl0eEgJKaEcdtBqhVDbL V2GMiWJSq2EGmiLlafF/D51jCBSNNSxkomy9yxoIbo8EeKGe6abFUKdaVzD1SNUpTnBD JlRPVDFtxZraxuZrunl+G9bMRu2X/bkbaZf1gQZuSO14q4mPthhoBiDTzaXR3Qq1VXTx LPlQ== X-Received: by 10.15.83.69 with SMTP id b45mr10354367eez.150.1371077708948; Wed, 12 Jun 2013 15:55:08 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id b7sm31069116eef.16.2013.06.12.15.55.07 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 12 Jun 2013 15:55:08 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 13 Jun 2013 00:54:59 +0200 Message-Id: <1371077699-30702-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1371077699-30702-1-git-send-email-daniel.vetter@ffwll.ch> References: <1371077699-30702-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQm5qbCSdev35+QTq5danIjT5CU/qcdJnAxWNb7lmNAXUC4QmMzxTzvXLebZLnk0QgO9FVrQ Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 3/3] drm/i915: explicitly set up PIPECONF (and gamma table) on haswell X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Again we don't really support different settings, so don't let the BIOS sneak stuff through. Since the motivation for this patch series is to ensure we have the correct gamma table mode selected also add the required write to the GAMMA_MODE register to select the 8bit legacy table. And since I find lowercase letters in #defines offensive, also bikeshed those. Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 6 +++--- drivers/gpu/drm/i915/intel_display.c | 7 ++++--- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 01e8783..8136b00 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3670,9 +3670,9 @@ #define _GAMMA_MODE_B 0x4ac80 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) #define GAMMA_MODE_MODE_MASK (3 << 0) -#define GAMMA_MODE_MODE_8bit (0 << 0) -#define GAMMA_MODE_MODE_10bit (1 << 0) -#define GAMMA_MODE_MODE_12bit (2 << 0) +#define GAMMA_MODE_MODE_8BIT (0 << 0) +#define GAMMA_MODE_MODE_10BIT (1 << 0) +#define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* interrupts */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4ca0273..e1184eb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5393,13 +5393,11 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; uint32_t val; - val = I915_READ(PIPECONF(cpu_transcoder)); + val = 0; - val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); if (intel_crtc->config.dither) val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); - val &= ~PIPECONF_INTERLACE_MASK_HSW; if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) val |= PIPECONF_INTERLACED_ILK; else @@ -5407,6 +5405,9 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) I915_WRITE(PIPECONF(cpu_transcoder), val); POSTING_READ(PIPECONF(cpu_transcoder)); + + I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); + POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); } static bool ironlake_compute_clocks(struct drm_crtc *crtc,