From patchwork Tue Jun 25 12:27:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2776301 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7EB57C0AB1 for ; Tue, 25 Jun 2013 12:27:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2375E201DE for ; Tue, 25 Jun 2013 12:27:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D426B201BD for ; Tue, 25 Jun 2013 12:27:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB366E61B4 for ; Tue, 25 Jun 2013 05:27:29 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id B9A9FE5D38 for ; Tue, 25 Jun 2013 05:27:17 -0700 (PDT) Received: by mail-ea0-f177.google.com with SMTP id j14so6671909eak.8 for ; Tue, 25 Jun 2013 05:27:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=rTDuPaoWFeTWr9r1L7DOF0f3rljIOvVjh/tYswDlBYY=; b=OFlc1A+nYF0wLXjhGV7LXkP/T54y5NcRevLZKmkFOmKHMcsMK+TtnTaWFxRF4wrtZx t4/x0LgBC9JJrNiYeLFvqYCWhxd8vGgH9WQoBfNcwDvN8gnXAO2a+NiUWhICydQNMg0r yIlfS6vx8tMDDrHbfxS/KZt9dFnXjUbOjdfcY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=rTDuPaoWFeTWr9r1L7DOF0f3rljIOvVjh/tYswDlBYY=; b=C3rIIggKAnfsZYNoZlVdpNlehFAOTQLT4y/sAIbPWl/qfwrwi+/4dfAlAgkSNLIiDK CL77x1I/Zwyv4/w+ObYMNDiK1SE/aPRNtmQn0oB95I1nuwhHSOX4ihTyvhHcLKX21FOx AiCWG0FBZbrAzfB5kGkS9ITm22sNL152B40fgl0pzso9rAHVdkHXOt7OkrxR8Qo6iCJB /Ec8NT7RLFtkf6mQ4mqIbVjr++8/9tD9PySY+w1p/uSHje8nnEqWdBRPzXCi57A2U31t YTVlNXbvAJ8VUfsvMcgXsQPWLLG4rC47f7iw43VvyS6727Oflb3JRqOZv8tnQK8AKK1t Th6g== X-Received: by 10.14.8.197 with SMTP id 45mr17598517eer.66.1372163236910; Tue, 25 Jun 2013 05:27:16 -0700 (PDT) Received: from natalie.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id w43sm35630249eez.6.2013.06.25.05.27.15 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 25 Jun 2013 05:27:16 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 25 Jun 2013 14:27:09 +0200 Message-Id: <1372163229-21087-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1371037046-3732-10-git-send-email-daniel.vetter@ffwll.ch> References: <1371037046-3732-10-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQl+cwvC10r0GR75kSgFO0+g/kCwOLJnkTaNiJT1mekyBjLbs5EI4STSI+Mf5G6mwf8ndHc0 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: extract ibx_display_interrupt_update X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This way all changes to SDEIMR all go through the same function, with the exception of the (single-threaded) setup/teardown code. For paranoia again add an assert_spin_locked. v2: For even more paranoia also sprinkle a spinlock assert over cpt_can_enable_serr_int since we need to have that one there, too. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 44 ++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 033132b..363caab 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -137,6 +137,8 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev) enum pipe pipe; struct intel_crtc *crtc; + assert_spin_locked(&dev_priv->irq_lock); + for_each_pipe(pipe) { crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); @@ -179,6 +181,20 @@ static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, } } +static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, + uint32_t interrupt_mask, + uint32_t enabled_irq_mask) +{ + uint32_t sdeimr = I915_READ(SDEIMR); + sdeimr &= ~interrupt_mask; + sdeimr |= ~enabled_irq_mask; + + assert_spin_locked(&dev_priv->irq_lock); + + I915_WRITE(SDEIMR, sdeimr); + POSTING_READ(SDEIMR); +} + static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc, bool enable) { @@ -187,12 +203,8 @@ static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc, uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; - if (enable) - I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit); - else - I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit); - - POSTING_READ(SDEIMR); + ibx_display_interrupt_update(dev_priv, bit, + enable ? bit : 0); } static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, @@ -208,13 +220,10 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN | SERR_INT_TRANS_B_FIFO_UNDERRUN | SERR_INT_TRANS_C_FIFO_UNDERRUN); - - I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT); - } else { - I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT); } - POSTING_READ(SDEIMR); + ibx_display_interrupt_update(dev_priv, SDE_ERROR_CPT, + enable ? SDE_ERROR_CPT : 0); } /** @@ -2588,22 +2597,21 @@ static void ibx_hpd_irq_setup(struct drm_device *dev) drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; struct drm_mode_config *mode_config = &dev->mode_config; struct intel_encoder *intel_encoder; - u32 mask = ~I915_READ(SDEIMR); - u32 hotplug; + u32 hotplug_irqs, hotplug, enabled_irqs = 0; if (HAS_PCH_IBX(dev)) { - mask &= ~SDE_HOTPLUG_MASK; + hotplug_irqs = SDE_HOTPLUG_MASK; list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) - mask |= hpd_ibx[intel_encoder->hpd_pin]; + enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; } else { - mask &= ~SDE_HOTPLUG_MASK_CPT; + hotplug_irqs = SDE_HOTPLUG_MASK_CPT; list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) - mask |= hpd_cpt[intel_encoder->hpd_pin]; + enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; } - I915_WRITE(SDEIMR, ~mask); + ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); /* * Enable digital hotplug on the PCH, and configure the DP short pulse