@@ -977,7 +977,8 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = HAS_LLC(dev);
break;
case I915_PARAM_HAS_ALIASING_PPGTT:
- value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
+ if (intel_enable_ppgtt(dev) && dev_priv->mm.aliasing_ppgtt)
+ value = 1;
break;
case I915_PARAM_HAS_WAIT_TIMEOUT:
value = 1;
@@ -4220,7 +4220,11 @@ int i915_gem_init(struct drm_device *dev)
DRM_DEBUG_DRIVER("allow wake ack timed out\n");
}
- if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
+ /* NB: In order to keep the code paths for all platforms with PPGTT the
+ * same, we run through this next section regardless, but don't actually
+ * enable the PPGTT via GFX_MODE.
+ */
+ if (HAS_ALIASING_PPGTT(dev)) {
struct i915_hw_ppgtt *ppgtt;
i915_gem_setup_global_gtt(dev, 0, dev_priv->gtt.mappable_end,
@@ -154,7 +154,9 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
ecochk = I915_READ(GAM_ECOCHK);
I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
ECOCHK_PPGTT_CACHE64B);
- I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+ if (intel_enable_ppgtt(dev))
+ I915_WRITE(GFX_MODE,
+ _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
} else if (INTEL_INFO(dev)->gen >= 7) {
uint32_t ecochk, ecobits;
This will allow us to use the same code paths whether or not we have PPGTT actually turned on. It will do all but actually enable the bits that tell the HW to use PPGTT. This patch also will help tie together contexts and PPGTT in the next patch. That patch wants to disable contexts if there is no PPGTT, and we disable PPGTT on gen6 with VT-D. Since Mesa depends on gen6+ having HW contexts, this is a requirement. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_dma.c | 3 ++- drivers/gpu/drm/i915/i915_gem.c | 6 +++++- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++- 3 files changed, 10 insertions(+), 3 deletions(-)