| Message ID | 1372395546-15728-1-git-send-email-xiong.y.zhang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 28, 2013 at 12:59:06PM +0800, Xiong Zhang wrote: > On DevCPT, the control register for Transcoder DP Sync Polarity is > TRANS_DP_CTL, not DP_CTL. > Without this patch, Many call trace occur on CPT machine with DP monitor. > The call trace is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X) > > v2: use intel-crtc to simple patch, suggested by Daniel. > > Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Queued for -next (with some tiny bikeshedding), thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/intel_dp.c | 35 +++++++++++++++++++++++++---------- > 1 file changed, 25 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 8708a0c..c3ff8ac 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1324,20 +1324,35 @@ static void intel_dp_get_config(struct intel_encoder *encoder, > struct intel_crtc_config *pipe_config) > { > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > - struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > u32 tmp, flags = 0; > + struct drm_device *dev = encoder->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + enum port port = dp_to_dig_port(intel_dp)->port; > + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > > - tmp = I915_READ(intel_dp->output_reg); > + if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { > + tmp = I915_READ(intel_dp->output_reg); > + if (tmp & DP_SYNC_HS_HIGH) > + flags |= DRM_MODE_FLAG_PHSYNC; > + else > + flags |= DRM_MODE_FLAG_NHSYNC; > > - if (tmp & DP_SYNC_HS_HIGH) > - flags |= DRM_MODE_FLAG_PHSYNC; > - else > - flags |= DRM_MODE_FLAG_NHSYNC; > + if (tmp & DP_SYNC_VS_HIGH) > + flags |= DRM_MODE_FLAG_PVSYNC; > + else > + flags |= DRM_MODE_FLAG_NVSYNC; > + } else { > + tmp = I915_READ(TRANS_DP_CTL(intel_crtc->pipe)); > + if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) > + flags |= DRM_MODE_FLAG_PHSYNC; > + else > + flags |= DRM_MODE_FLAG_NHSYNC; > > - if (tmp & DP_SYNC_VS_HIGH) > - flags |= DRM_MODE_FLAG_PVSYNC; > - else > - flags |= DRM_MODE_FLAG_NVSYNC; > + if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) > + flags |= DRM_MODE_FLAG_PVSYNC; > + else > + flags |= DRM_MODE_FLAG_NVSYNC; > + } > > pipe_config->adjusted_mode.flags |= flags; > } > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8708a0c..c3ff8ac 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1324,20 +1324,35 @@ static void intel_dp_get_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); - struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; u32 tmp, flags = 0; + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum port port = dp_to_dig_port(intel_dp)->port; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - tmp = I915_READ(intel_dp->output_reg); + if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { + tmp = I915_READ(intel_dp->output_reg); + if (tmp & DP_SYNC_HS_HIGH) + flags |= DRM_MODE_FLAG_PHSYNC; + else + flags |= DRM_MODE_FLAG_NHSYNC; - if (tmp & DP_SYNC_HS_HIGH) - flags |= DRM_MODE_FLAG_PHSYNC; - else - flags |= DRM_MODE_FLAG_NHSYNC; + if (tmp & DP_SYNC_VS_HIGH) + flags |= DRM_MODE_FLAG_PVSYNC; + else + flags |= DRM_MODE_FLAG_NVSYNC; + } else { + tmp = I915_READ(TRANS_DP_CTL(intel_crtc->pipe)); + if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) + flags |= DRM_MODE_FLAG_PHSYNC; + else + flags |= DRM_MODE_FLAG_NHSYNC; - if (tmp & DP_SYNC_VS_HIGH) - flags |= DRM_MODE_FLAG_PVSYNC; - else - flags |= DRM_MODE_FLAG_NVSYNC; + if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) + flags |= DRM_MODE_FLAG_PVSYNC; + else + flags |= DRM_MODE_FLAG_NVSYNC; + } pipe_config->adjusted_mode.flags |= flags; }
On DevCPT, the control register for Transcoder DP Sync Polarity is TRANS_DP_CTL, not DP_CTL. Without this patch, Many call trace occur on CPT machine with DP monitor. The call trace is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X) v2: use intel-crtc to simple patch, suggested by Daniel. Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-)