| Message ID | 1372973734-7601-15-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jul 04, 2013 at 11:35:34PM +0200, Daniel Vetter wrote: > At the moment we have the following interrupt enabling sequence: > 1. irq preinstall hook > 2. enabling the interrupt handler and calling irq postinstall hook > 3. enable rps interrupts from the async work > > And the folliwing disable sequence: > 1. disabling the interrupt handler and calling the uninstall hook > 2. disabling the rps interrupt > > Since the postinstall hook now always sets up PMIIR, PMIER and PMIMR > to known-good states there no way for an interrupt to sneak in in the > enable sequence, so we can reinstate the WARN lost in > > commit eda63ffb906c2fb3b609a0e87aeb63c0f25b9e6b > Author: Ben Widawsky <ben@bwidawsk.net> > Date: Tue May 28 19:22:26 2013 -0700 > > drm/i915: Add PM regs to pre/post install > > Note that there's some room for future cleanups since most of the > interrupt register clearing in the disable function is rather > redundant. But that's better done in follow-up patches, if at all. > > Cc: Ben Widawsky <ben@bwidawsk.net> > Reviewed-by: Ben Widawsky <ben@bwidawsk.net> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Ok, final 4 patches from this series are now merged. Thanks everyone for the review. -Daniel > --- > drivers/gpu/drm/i915/intel_pm.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 787a528..bc5aae0 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3193,9 +3193,7 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > spin_lock_irq(&dev_priv->irq_lock); > - /* FIXME: Our interrupt enabling sequence is bonghits. > - * dev_priv->rps.pm_iir really should be 0 here. */ > - dev_priv->rps.pm_iir = 0; > + WARN_ON(dev_priv->rps.pm_iir); > I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); > I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); > spin_unlock_irq(&dev_priv->irq_lock); > -- > 1.8.1.4 >
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 787a528..bc5aae0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3193,9 +3193,7 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; spin_lock_irq(&dev_priv->irq_lock); - /* FIXME: Our interrupt enabling sequence is bonghits. - * dev_priv->rps.pm_iir really should be 0 here. */ - dev_priv->rps.pm_iir = 0; + WARN_ON(dev_priv->rps.pm_iir); I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); spin_unlock_irq(&dev_priv->irq_lock);
At the moment we have the following interrupt enabling sequence: 1. irq preinstall hook 2. enabling the interrupt handler and calling irq postinstall hook 3. enable rps interrupts from the async work And the folliwing disable sequence: 1. disabling the interrupt handler and calling the uninstall hook 2. disabling the rps interrupt Since the postinstall hook now always sets up PMIIR, PMIER and PMIMR to known-good states there no way for an interrupt to sneak in in the enable sequence, so we can reinstate the WARN lost in commit eda63ffb906c2fb3b609a0e87aeb63c0f25b9e6b Author: Ben Widawsky <ben@bwidawsk.net> Date: Tue May 28 19:22:26 2013 -0700 drm/i915: Add PM regs to pre/post install Note that there's some room for future cleanups since most of the interrupt register clearing in the disable function is rather redundant. But that's better done in follow-up patches, if at all. Cc: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_pm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)