From patchwork Fri Jul 5 08:57:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 2824034 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B3C019F7D6 for ; Fri, 5 Jul 2013 08:58:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B216120158 for ; Fri, 5 Jul 2013 08:58:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 695BD20153 for ; Fri, 5 Jul 2013 08:58:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6171BE6735 for ; Fri, 5 Jul 2013 01:58:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id ACB84E6755 for ; Fri, 5 Jul 2013 01:58:02 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 05 Jul 2013 01:55:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.87,1000,1363158000"; d="scan'208"; a="340851160" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.168]) by orsmga001.jf.intel.com with SMTP; 05 Jul 2013 01:57:54 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Jul 2013 11:57:53 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Jul 2013 11:57:13 +0300 Message-Id: <1373014667-19484-2-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1373014667-19484-1-git-send-email-ville.syrjala@linux.intel.com> References: <1373014667-19484-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/35] drm/i915: Add scaled paramater to update_sprite_watermarks() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Fro calculating watermarks we want to know whether sprites are scaled. Pass that information to update_sprite_watermarks() so that eventually we may do some watermark pre-computing. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_drv.h | 7 ++++--- drivers/gpu/drm/i915/intel_pm.c | 13 +++++++------ drivers/gpu/drm/i915/intel_sprite.c | 11 +++++++---- 4 files changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fd0f589..99eb980 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -361,7 +361,7 @@ struct drm_i915_display_funcs { void (*update_wm)(struct drm_device *dev); void (*update_sprite_wm)(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, - bool enable); + bool enable, bool scaled); void (*modeset_global_resources)(struct drm_device *dev); /* Returns the active state of the crtc, and if the crtc is active, * fills out the pipe-config with the hw state. */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5dfc1a0..3371ecc 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -353,7 +353,8 @@ struct intel_plane { * for the watermark calculations. Currently only Haswell uses this. */ struct { - bool enable; + bool enabled; + bool scaled; uint8_t bytes_per_pixel; uint32_t horiz_pixels; } wm; @@ -772,8 +773,8 @@ extern void intel_ddi_init(struct drm_device *dev, enum port port); /* For use by IVB LP watermark workaround in intel_sprite.c */ extern void intel_update_watermarks(struct drm_device *dev); extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, - uint32_t sprite_width, - int pixel_size, bool enable); + uint32_t sprite_width, int pixel_size, + bool enabled, bool scaled); extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, unsigned int tiling_mode, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7cfd3b7..beca186 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2388,7 +2388,7 @@ static void hsw_compute_wm_parameters(struct drm_device *dev, pipe = intel_plane->pipe; p = ¶ms[pipe]; - p->sprite_enabled = intel_plane->wm.enable; + p->sprite_enabled = intel_plane->wm.enabled; p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel; p->spr_horiz_pixels = intel_plane->wm.horiz_pixels; @@ -2616,7 +2616,7 @@ static void haswell_update_wm(struct drm_device *dev) static void haswell_update_sprite_wm(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, - bool enable) + bool enabled, bool scaled) { struct drm_plane *plane; @@ -2624,7 +2624,8 @@ static void haswell_update_sprite_wm(struct drm_device *dev, int pipe, struct intel_plane *intel_plane = to_intel_plane(plane); if (intel_plane->pipe == pipe) { - intel_plane->wm.enable = enable; + intel_plane->wm.enabled = enabled; + intel_plane->wm.scaled = scaled; intel_plane->wm.horiz_pixels = sprite_width + 1; intel_plane->wm.bytes_per_pixel = pixel_size; break; @@ -2712,7 +2713,7 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, - bool enable) + bool enable, bool scaled) { struct drm_i915_private *dev_priv = dev->dev_private; int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ @@ -2835,13 +2836,13 @@ void intel_update_watermarks(struct drm_device *dev) void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, uint32_t sprite_width, int pixel_size, - bool enable) + bool enable, bool scaled) { struct drm_i915_private *dev_priv = dev->dev_private; if (dev_priv->display.update_sprite_wm) dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, - pixel_size, enable); + pixel_size, enable, scaled); } static struct drm_i915_gem_object * diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 1fa5612..5a1f3fd 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -114,7 +114,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, crtc_w--; crtc_h--; - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true); + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, + src_w != crtc_w || src_h != crtc_h); I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); @@ -268,7 +269,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, crtc_w--; crtc_h--; - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true); + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, + src_w != crtc_w || src_h != crtc_h); /* * IVB workaround: must disable low power watermarks for at least @@ -335,7 +337,7 @@ ivb_disable_plane(struct drm_plane *plane) dev_priv->sprite_scaling_enabled &= ~(1 << pipe); - intel_update_sprite_watermarks(dev, pipe, 0, 0, false); + intel_update_sprite_watermarks(dev, pipe, 0, 0, false, false); /* potentially re-enable LP watermarks */ if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) @@ -455,7 +457,8 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, crtc_w--; crtc_h--; - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true); + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, + src_w != crtc_w || src_h != crtc_h); dvsscale = 0; if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)