From patchwork Fri Jul 5 08:57:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 2824058 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0428DBF4A1 for ; Fri, 5 Jul 2013 09:09:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D51FF20158 for ; Fri, 5 Jul 2013 09:09:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id DB5DD20138 for ; Fri, 5 Jul 2013 09:08:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6E72E616E for ; Fri, 5 Jul 2013 02:08:59 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 81F26E6752 for ; Fri, 5 Jul 2013 01:59:10 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 05 Jul 2013 01:59:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.87,1000,1363158000"; d="scan'208"; a="360862082" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.168]) by fmsmga001.fm.intel.com with SMTP; 05 Jul 2013 02:00:05 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Jul 2013 11:59:07 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Jul 2013 11:57:35 +0300 Message-Id: <1373014667-19484-24-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1373014667-19484-1-git-send-email-ville.syrjala@linux.intel.com> References: <1373014667-19484-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 23/35] drm/i915; Pull some watermarks state into a separate structure X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä There is a bunch of global state that needs to be considered when checking watermarks for validity. Move most of that to a new structure intel_wm_config, to avoid having to pass around so many variables. One notable thing left out is the DDB partitioning information, since we often anyway need to check the same watermarks against both 1/2 and 5/6 DDB partitioning layouts. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 48 +++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2bdb0ae..43d05db 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2174,6 +2174,14 @@ struct hsw_wm_values { bool enable_fbc_wm; }; +/* used in computing the new watermarks state */ +struct intel_wm_config { + unsigned int pipes_active; + bool sprites_enabled; + bool sprites_scaled; + bool fbc_wm_enabled; +}; + /* For both WM_PIPE and WM_LP. */ static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params, uint32_t mem_value, @@ -2258,8 +2266,7 @@ static unsigned int ilk_display_fifo_size(const struct drm_device *dev) /* Calculate the maximum primary/sprite plane watermark */ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, int level, - unsigned int pipes_active, - bool sprite_enabled, + const struct intel_wm_config *config, enum intel_ddb_partitioning ddb_partitioning, bool is_sprite) { @@ -2267,11 +2274,11 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, unsigned int max; /* if sprites aren't enabled, sprites get nothing */ - if (is_sprite && !sprite_enabled) + if (is_sprite && !config->sprites_enabled) return 0; /* HSW allows LP1+ watermarks even with multiple pipes */ - if (level == 0 || pipes_active > 1) { + if (level == 0 || config->pipes_active > 1) { fifo_size /= INTEL_INFO(dev)->num_pipes; /* @@ -2283,7 +2290,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, fifo_size /= 2; } - if (sprite_enabled) { + if (config->sprites_enabled) { /* level 0 is always calculated with 1:1 split */ if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { if (is_sprite) @@ -2310,10 +2317,11 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, /* Calculate the maximum cursor plane watermark */ static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, - int level, unsigned int pipes_active) + int level, + const struct intel_wm_config *config) { /* HSW LP1+ watermarks w/ multiple pipes */ - if (level > 0 && pipes_active > 1) + if (level > 0 && config->pipes_active > 1) return 64; /* othwewise just report max that registers can hold */ @@ -2332,16 +2340,13 @@ static unsigned int ilk_fbc_wm_max(void) static void ilk_wm_max(struct drm_device *dev, int level, - unsigned int pipes_active, - bool sprite_enabled, + const struct intel_wm_config *config, enum intel_ddb_partitioning ddb_partitioning, struct hsw_wm_maximums *max) { - max->pri = ilk_plane_wm_max(dev, level, pipes_active, - sprite_enabled, ddb_partitioning, false); - max->spr = ilk_plane_wm_max(dev, level, pipes_active, - sprite_enabled, ddb_partitioning, true); - max->cur = ilk_cursor_wm_max(dev, level, pipes_active); + max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); + max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); + max->cur = ilk_cursor_wm_max(dev, level, config); max->fbc = ilk_fbc_wm_max(); } @@ -2567,7 +2572,7 @@ static void hsw_compute_wm_parameters(struct drm_device *dev, struct drm_crtc *crtc; struct drm_plane *plane; enum pipe pipe; - int pipes_active = 0, sprites_enabled = 0; + struct intel_wm_config config = {}; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); @@ -2580,7 +2585,7 @@ static void hsw_compute_wm_parameters(struct drm_device *dev, if (!p->active) continue; - pipes_active++; + config.pipes_active++; p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal; p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); @@ -2602,17 +2607,14 @@ static void hsw_compute_wm_parameters(struct drm_device *dev, p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel; p->spr_horiz_pixels = intel_plane->wm.horiz_pixels; - if (p->sprite_enabled) - sprites_enabled++; + config.sprites_enabled |= p->sprite_enabled; } - ilk_wm_max(dev, 1, pipes_active, sprites_enabled, - INTEL_DDB_PART_1_2, lp_max_1_2); + ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2); /* 5/6 split only in single pipe config on IVB+ */ - if (INTEL_INFO(dev)->gen >= 7 && pipes_active <= 1) - ilk_wm_max(dev, 1, pipes_active, sprites_enabled, - INTEL_DDB_PART_5_6, lp_max_5_6); + if (INTEL_INFO(dev)->gen >= 7 && config.pipes_active <= 1) + ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6); else *lp_max_5_6 = *lp_max_1_2; }