| Message ID | 1373014667-19484-3-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2013/7/5 <ville.syrjala@linux.intel.com>: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Don't subtract one from the sprite width before watermark calculations. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Looks like the bikeshed I just gave about the "scaled" variable would cause the need to rebase this patch. So just forget it :) > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++--------- > 2 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index beca186..db548a1 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2626,7 +2626,7 @@ static void haswell_update_sprite_wm(struct drm_device *dev, int pipe, > if (intel_plane->pipe == pipe) { > intel_plane->wm.enabled = enabled; > intel_plane->wm.scaled = scaled; > - intel_plane->wm.horiz_pixels = sprite_width + 1; > + intel_plane->wm.horiz_pixels = sprite_width; > intel_plane->wm.bytes_per_pixel = pixel_size; > break; > } > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index 5a1f3fd..d7fca56 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -108,15 +108,15 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, > > sprctl |= SP_ENABLE; > > + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, > + src_w != crtc_w || src_h != crtc_h); > + > /* Sizes are 0 based */ > src_w--; > src_h--; > crtc_w--; > crtc_h--; > > - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, > - src_w != crtc_w || src_h != crtc_h); > - > I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); > I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); > > @@ -263,15 +263,15 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, > if (IS_HASWELL(dev)) > sprctl |= SPRITE_PIPE_CSC_ENABLE; > > + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, > + src_w != crtc_w || src_h != crtc_h); > + > /* Sizes are 0 based */ > src_w--; > src_h--; > crtc_w--; > crtc_h--; > > - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, > - src_w != crtc_w || src_h != crtc_h); > - > /* > * IVB workaround: must disable low power watermarks for at least > * one frame before enabling scaling. LP watermarks can be re-enabled > @@ -451,15 +451,15 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, > dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ > dvscntr |= DVS_ENABLE; > > + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, > + src_w != crtc_w || src_h != crtc_h); > + > /* Sizes are 0 based */ > src_w--; > src_h--; > crtc_w--; > crtc_h--; > > - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, > - src_w != crtc_w || src_h != crtc_h); > - > dvsscale = 0; > if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) > dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index beca186..db548a1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2626,7 +2626,7 @@ static void haswell_update_sprite_wm(struct drm_device *dev, int pipe, if (intel_plane->pipe == pipe) { intel_plane->wm.enabled = enabled; intel_plane->wm.scaled = scaled; - intel_plane->wm.horiz_pixels = sprite_width + 1; + intel_plane->wm.horiz_pixels = sprite_width; intel_plane->wm.bytes_per_pixel = pixel_size; break; } diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 5a1f3fd..d7fca56 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -108,15 +108,15 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, sprctl |= SP_ENABLE; + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, + src_w != crtc_w || src_h != crtc_h); + /* Sizes are 0 based */ src_w--; src_h--; crtc_w--; crtc_h--; - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, - src_w != crtc_w || src_h != crtc_h); - I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); @@ -263,15 +263,15 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, if (IS_HASWELL(dev)) sprctl |= SPRITE_PIPE_CSC_ENABLE; + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, + src_w != crtc_w || src_h != crtc_h); + /* Sizes are 0 based */ src_w--; src_h--; crtc_w--; crtc_h--; - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, - src_w != crtc_w || src_h != crtc_h); - /* * IVB workaround: must disable low power watermarks for at least * one frame before enabling scaling. LP watermarks can be re-enabled @@ -451,15 +451,15 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ dvscntr |= DVS_ENABLE; + intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, + src_w != crtc_w || src_h != crtc_h); + /* Sizes are 0 based */ src_w--; src_h--; crtc_w--; crtc_h--; - intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true, - src_w != crtc_w || src_h != crtc_h); - dvsscale = 0; if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;