| Message ID | 1373014667-19484-32-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2013/7/5 <ville.syrjala@linux.intel.com>: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The linetime watermarks don't change, except when doing a full modeset, > so having them as part of the full dynamic watermarks code is pointless. > > Just move the linetime watermark setup to occur just before enabling the > pipe on HSW, and leave it alone after that. You're kinda reverting a patch I wrote earlier. One of my concerns is that I wanted to make sure that when we update the linetime watermarks all WM_LP watermarks are zero. The order in which we write the LP registers is important, so I wanted to make sure we always did it correctly. I see hsw_write_wm_values got killed, so now it's harder to check if we're writing the registers in the right order. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_drv.h | 1 - > drivers/gpu/drm/i915/intel_pm.c | 32 -------------------------------- > 3 files changed, 22 insertions(+), 33 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 54216d1..7ad66de 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3320,6 +3320,26 @@ static void hsw_disable_ips(struct intel_crtc *crtc) > intel_wait_for_vblank(dev, crtc->pipe); > } > > +static void > +hsw_setup_linetime_wm(struct drm_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = crtc->dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; > + u32 linetime, ips_linetime; > + > + /* The WM are computed with base on how long it takes to fill a single > + * row at the given clock rate, multiplied by 8. > + * */ > + linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock); > + ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, > + intel_ddi_get_cdclk_freq(dev_priv)); > + > + I915_WRITE(PIPE_WM_LINETIME(intel_crtc->pipe), > + PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | > + PIPE_WM_LINETIME_TIME(linetime)); > +} > + > static void haswell_crtc_enable(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > @@ -3360,6 +3380,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > intel_ddi_set_pipe_settings(crtc); > intel_ddi_enable_transcoder_func(crtc); > > + hsw_setup_linetime_wm(crtc); > + > intel_update_watermarks(crtc); > intel_enable_pipe(dev_priv, pipe, > intel_crtc->config.has_pch_encoder); > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index a5c15ab..d7996e0 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -297,7 +297,6 @@ struct intel_pipe_wm { > bool sprites_enabled; > bool sprites_scaled; > bool fbc_wm_enabled; > - uint32_t linetime; > struct intel_wm_level wm[5]; > }; > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7fd922dc..d2cbc94 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2342,10 +2342,6 @@ static void ilk_program_watermarks(struct drm_device *dev) > wm->spr_val << WM0_PIPE_SPRITE_SHIFT | > wm->cur_val); > > - if (INTEL_INFO(dev)->gen > 7 || IS_HASWELL(dev)) > - I915_WRITE(PIPE_WM_LINETIME(intel_crtc->pipe), > - pipe_wm->linetime); > - > intel_crtc->wm.hw = *wm; > } > > @@ -2437,9 +2433,6 @@ static void ilk_program_watermarks(struct drm_device *dev) > } > } > > -static uint32_t > -hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc); > - > static int ilk_max_wm_level(const struct drm_device *dev, > const struct intel_pipe_wm *pipe_wm) > { > @@ -2512,9 +2505,6 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc, > for (level = 0; level <= max_level; level++) > ilk_compute_wm_level(dev_priv, level, &p, &pipe_wm->wm[level]); > > - if (IS_HASWELL(dev)) > - pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); > - > ilk_wm_max(dev, 0, &config, false, &max); > > /* At least LP0 must be valid */ > @@ -2597,28 +2587,6 @@ void ilk_update_pipe_wm(struct drm_device *dev, enum pipe pipe) > spin_unlock_irqrestore(&dev_priv->wm.lock, flags); > } > > -static uint32_t > -hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) > -{ > - struct drm_i915_private *dev_priv = dev->dev_private; > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; > - u32 linetime, ips_linetime; > - > - if (!intel_crtc_active(crtc)) > - return 0; > - > - /* The WM are computed with base on how long it takes to fill a single > - * row at the given clock rate, multiplied by 8. > - * */ > - linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock); > - ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, > - intel_ddi_get_cdclk_freq(dev_priv)); > - > - return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | > - PIPE_WM_LINETIME_TIME(linetime); > -} > - > static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) > { > struct drm_i915_private *dev_priv = dev->dev_private; > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 54216d1..7ad66de 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3320,6 +3320,26 @@ static void hsw_disable_ips(struct intel_crtc *crtc) intel_wait_for_vblank(dev, crtc->pipe); } +static void +hsw_setup_linetime_wm(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = crtc->dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; + u32 linetime, ips_linetime; + + /* The WM are computed with base on how long it takes to fill a single + * row at the given clock rate, multiplied by 8. + * */ + linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock); + ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, + intel_ddi_get_cdclk_freq(dev_priv)); + + I915_WRITE(PIPE_WM_LINETIME(intel_crtc->pipe), + PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | + PIPE_WM_LINETIME_TIME(linetime)); +} + static void haswell_crtc_enable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -3360,6 +3380,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_ddi_set_pipe_settings(crtc); intel_ddi_enable_transcoder_func(crtc); + hsw_setup_linetime_wm(crtc); + intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, intel_crtc->config.has_pch_encoder); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a5c15ab..d7996e0 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -297,7 +297,6 @@ struct intel_pipe_wm { bool sprites_enabled; bool sprites_scaled; bool fbc_wm_enabled; - uint32_t linetime; struct intel_wm_level wm[5]; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7fd922dc..d2cbc94 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2342,10 +2342,6 @@ static void ilk_program_watermarks(struct drm_device *dev) wm->spr_val << WM0_PIPE_SPRITE_SHIFT | wm->cur_val); - if (INTEL_INFO(dev)->gen > 7 || IS_HASWELL(dev)) - I915_WRITE(PIPE_WM_LINETIME(intel_crtc->pipe), - pipe_wm->linetime); - intel_crtc->wm.hw = *wm; } @@ -2437,9 +2433,6 @@ static void ilk_program_watermarks(struct drm_device *dev) } } -static uint32_t -hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc); - static int ilk_max_wm_level(const struct drm_device *dev, const struct intel_pipe_wm *pipe_wm) { @@ -2512,9 +2505,6 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc, for (level = 0; level <= max_level; level++) ilk_compute_wm_level(dev_priv, level, &p, &pipe_wm->wm[level]); - if (IS_HASWELL(dev)) - pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); - ilk_wm_max(dev, 0, &config, false, &max); /* At least LP0 must be valid */ @@ -2597,28 +2587,6 @@ void ilk_update_pipe_wm(struct drm_device *dev, enum pipe pipe) spin_unlock_irqrestore(&dev_priv->wm.lock, flags); } -static uint32_t -hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; - u32 linetime, ips_linetime; - - if (!intel_crtc_active(crtc)) - return 0; - - /* The WM are computed with base on how long it takes to fill a single - * row at the given clock rate, multiplied by 8. - * */ - linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock); - ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, - intel_ddi_get_cdclk_freq(dev_priv)); - - return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | - PIPE_WM_LINETIME_TIME(linetime); -} - static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) { struct drm_i915_private *dev_priv = dev->dev_private;