| Message ID | 1373366437-15517-1-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jul 9, 2013 at 12:40 PM, Imre Deak <imre.deak@intel.com> wrote: > DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which > the driver will treat as an invalid value and use 1.62Gbps instead. Fix > this by capping to 2.7Gbps anything beyond the DP 1.1 bandwidth range. > > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 11eb697..c6dd61f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -71,11 +71,16 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) > { > int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; > > + if (max_link_bw > DP_LINK_BW_2_7) > + return DP_LINK_BW_2_7; > + > switch (max_link_bw) { > case DP_LINK_BW_1_62: > case DP_LINK_BW_2_7: Shouldn't we just add a new case for 5.4 GHz and cap it appropriately. As is we'll eat any bogus value > BW_2_7 ... -Daniel > break; > default: > + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", > + max_link_bw); > max_link_bw = DP_LINK_BW_1_62; > break; > } > -- > 1.8.1.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
On Tue, 2013-07-09 at 14:35 +0200, Daniel Vetter wrote: > On Tue, Jul 9, 2013 at 12:40 PM, Imre Deak <imre.deak@intel.com> wrote: > > DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which > > the driver will treat as an invalid value and use 1.62Gbps instead. Fix > > this by capping to 2.7Gbps anything beyond the DP 1.1 bandwidth range. > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/intel_dp.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 11eb697..c6dd61f 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -71,11 +71,16 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) > > { > > int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; > > > > + if (max_link_bw > DP_LINK_BW_2_7) > > + return DP_LINK_BW_2_7; > > + > > switch (max_link_bw) { > > case DP_LINK_BW_1_62: > > case DP_LINK_BW_2_7: > > Shouldn't we just add a new case for 5.4 GHz and cap it appropriately. > As is we'll eat any bogus value > BW_2_7 ... I thought that this is more future proof. We would add proper 5.4 support as part of a bigger 1.2 enabling work, having there a similar capping to BW_5_4 for post DP 1.2 sinks. > -Daniel > > > break; > > default: > > + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", > > + max_link_bw); > > max_link_bw = DP_LINK_BW_1_62; > > break; > > } > > -- > > 1.8.1.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
On Tue, Jul 09, 2013 at 01:40:37PM +0300, Imre Deak wrote: > DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which > the driver will treat as an invalid value and use 1.62Gbps instead. Fix > this by capping to 2.7Gbps anything beyond the DP 1.1 bandwidth range. Comments inline. > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 11eb697..c6dd61f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -71,11 +71,16 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) > { > int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; > > + if (max_link_bw > DP_LINK_BW_2_7) > + return DP_LINK_BW_2_7; > + > switch (max_link_bw) { I think putting it here is preferrable: case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ max_link_bw = DP_LINK_BW_2_7; break; Then we still get the WARN for unknown values greater than 0xa. > case DP_LINK_BW_1_62: > case DP_LINK_BW_2_7: > break; > default: > + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", > + max_link_bw); > max_link_bw = DP_LINK_BW_1_62; > break;
On Tue, Jul 09, 2013 at 03:47:42PM +0300, Imre Deak wrote: > On Tue, 2013-07-09 at 14:35 +0200, Daniel Vetter wrote: > > On Tue, Jul 9, 2013 at 12:40 PM, Imre Deak <imre.deak@intel.com> wrote: > > > DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which > > > the driver will treat as an invalid value and use 1.62Gbps instead. Fix > > > this by capping to 2.7Gbps anything beyond the DP 1.1 bandwidth range. > > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_dp.c | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > > index 11eb697..c6dd61f 100644 > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > @@ -71,11 +71,16 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) > > > { > > > int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; > > > > > > + if (max_link_bw > DP_LINK_BW_2_7) > > > + return DP_LINK_BW_2_7; > > > + > > > switch (max_link_bw) { > > > case DP_LINK_BW_1_62: > > > case DP_LINK_BW_2_7: > > > > Shouldn't we just add a new case for 5.4 GHz and cap it appropriately. > > As is we'll eat any bogus value > BW_2_7 ... > > I thought that this is more future proof. We would add proper 5.4 > support as part of a bigger 1.2 enabling work, having there a similar > capping to BW_5_4 for post DP 1.2 sinks. Presuming of course that they don't introduce a new low power low frequency update using a randomly high dpcd value of, for example, 0xf. Hence warning and going with the lowest supported value. -Chris
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 11eb697..c6dd61f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -71,11 +71,16 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) { int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; + if (max_link_bw > DP_LINK_BW_2_7) + return DP_LINK_BW_2_7; + switch (max_link_bw) { case DP_LINK_BW_1_62: case DP_LINK_BW_2_7: break; default: + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", + max_link_bw); max_link_bw = DP_LINK_BW_1_62; break; }
DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which the driver will treat as an invalid value and use 1.62Gbps instead. Fix this by capping to 2.7Gbps anything beyond the DP 1.1 bandwidth range. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 5 +++++ 1 file changed, 5 insertions(+)