From patchwork Tue Jul 9 12:44:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2825266 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 967ADC0AB2 for ; Tue, 9 Jul 2013 12:47:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5CAA520136 for ; Tue, 9 Jul 2013 12:47:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8DABD20121 for ; Tue, 9 Jul 2013 12:47:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5572CE6193 for ; Tue, 9 Jul 2013 05:47:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f43.google.com (mail-ee0-f43.google.com [74.125.83.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C291E5CD5 for ; Tue, 9 Jul 2013 05:47:02 -0700 (PDT) Received: by mail-ee0-f43.google.com with SMTP id l10so3539926eei.16 for ; Tue, 09 Jul 2013 05:47:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=ql9Fv2g6HCiThKSVP+YbWKXW97ohYlM48gAQ1ZPhENU=; b=ZEnRBIPk8kNDY/bM3KIDF2YUtgxap/rMmOp1MiUel9dFPi/3b3H/OVS+ZlffIUlkAZ Xhf6SOReYD0B3C0IowNB2XsvTfqDhYereXjGvJblnwQcZVhh3IahJMCVn6HZFQL9Yslf NVwWBydnz77OiCt9YdarEodH/rlKRDqrSjztI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ql9Fv2g6HCiThKSVP+YbWKXW97ohYlM48gAQ1ZPhENU=; b=e61EVmeTNkyWQVNbFKA9jy/bz4oBr6/Rz/QUsO/esiuUBJaVuFI2A5OerrcKkPdO2v igWWHO4HT8WDHdEm/ACWIX1xrtTU+Y/5XCsvDyb8299aE91ezi0HYUDfioA9qxHRkwC+ BlRmyk8TZp/kFUh/igEm1WlwIxwsnUiA+0ksrKSvMyRKh2TcB3DwpTgwvHhAS73alGvT 8KOQoQdH9oisMkwt1ixM1s2VRzyiMWHTSuhoGRvgaAjgNQ15OPiP8/Aio03M5SZKSMiU pG6VLVpUCpdTRe05ia15rCGcMG9al03e2jPkzdCnlRTqFrHrAteUYrRSAmnkh6oujCUN qGNA== X-Received: by 10.14.32.197 with SMTP id o45mr30810936eea.9.1373374021480; Tue, 09 Jul 2013 05:47:01 -0700 (PDT) Received: from gina.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id w43sm50825315eez.6.2013.07.09.05.46.59 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 09 Jul 2013 05:47:00 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 9 Jul 2013 14:44:26 +0200 Message-Id: <1373373867-28080-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <20130703084052.GI4573@cantiga.alporthouse.com> References: <20130703084052.GI4573@cantiga.alporthouse.com> X-Gm-Message-State: ALoCoQlOPFdXlnatLKmXAUNBlRPX1liptN79gIAzDRyIsuX+bKomVZB1EgQ607Ivm6Zd0Kyy+p7L Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/2] drm/i915: clean up media reset on gm45 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Originally I've thought that this fixes up the reset issues on my gm45, but that was just a red herring due to b0rked testing. Still I much prefer writing the right values (all other fields are reserved) instead of potentially dragging gunk around. Hence also clear the register to 0 after a reset. Note that Cspec is a bit confused and doesn't explicitly say that all the other bits in this register are "reserved, mbz" like usually. Instead they're marked as "r/o, default value = 0" which semantically amounts to the same thing. v2: Stop claiming this fixes anything and return 0 if successful instead of stack garbage. v3: Pimp the commit message to explain exactly why I think the docs allow us to ditch the rmw cycle, spurred by a discussion with Chris. Cc: Chris Wilson Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index e6dc81c..5400d2b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -798,28 +798,29 @@ static int i965_reset_complete(struct drm_device *dev) static int i965_do_reset(struct drm_device *dev) { int ret; - u8 gdrst; /* * Set the domains we want to reset (GRDOM/bits 2 and 3) as * well as the reset bit (GR/bit 0). Setting the GR bit * triggers the reset; when done, the hardware will clear it. */ - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); pci_write_config_byte(dev->pdev, I965_GDRST, - gdrst | GRDOM_RENDER | - GRDOM_RESET_ENABLE); + GRDOM_RENDER | GRDOM_RESET_ENABLE); ret = wait_for(i965_reset_complete(dev), 500); if (ret) return ret; /* We can't reset render&media without also resetting display ... */ - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); pci_write_config_byte(dev->pdev, I965_GDRST, - gdrst | GRDOM_MEDIA | - GRDOM_RESET_ENABLE); + GRDOM_MEDIA | GRDOM_RESET_ENABLE); - return wait_for(i965_reset_complete(dev), 500); + ret = wait_for(i965_reset_complete(dev), 500); + if (ret) + return ret; + + pci_write_config_byte(dev->pdev, I965_GDRST, 0); + + return 0; } static int ironlake_do_reset(struct drm_device *dev)