diff mbox

[v2] drm/i915: fix lane bandwidth capping for DP 1.2 sinks

Message ID 1373378726-18437-1-git-send-email-imre.deak@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Imre Deak July 9, 2013, 2:05 p.m. UTC
DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which
the driver will treat as an invalid value and use 1.62Gbps instead. Fix
this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw.

Also add a warning for reserved values.

v2:
- allow only bw values explicitly listed in the DP standard (Daniel,
  Chris)

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Daniel Vetter July 9, 2013, 2:36 p.m. UTC | #1
On Tue, Jul 09, 2013 at 05:05:26PM +0300, Imre Deak wrote:
> DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which
> the driver will treat as an invalid value and use 1.62Gbps instead. Fix
> this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw.
> 
> Also add a warning for reserved values.
> 
> v2:
> - allow only bw values explicitly listed in the DP standard (Daniel,
>   Chris)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

lgtm. Picked up for -fixes, thanks for the patch.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 11eb697..7db2cd7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -75,7 +75,12 @@  intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	case DP_LINK_BW_1_62:
 	case DP_LINK_BW_2_7:
 		break;
+	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
+		max_link_bw = DP_LINK_BW_2_7;
+		break;
 	default:
+		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
+		     max_link_bw);
 		max_link_bw = DP_LINK_BW_1_62;
 		break;
 	}