From patchwork Tue Jul 9 20:59:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2825447 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E3FC2C0AB2 for ; Tue, 9 Jul 2013 21:00:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0065320137 for ; Tue, 9 Jul 2013 21:00:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 18E692010B for ; Tue, 9 Jul 2013 21:00:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 84172E6288 for ; Tue, 9 Jul 2013 14:00:30 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f176.google.com (mail-ea0-f176.google.com [209.85.215.176]) by gabe.freedesktop.org (Postfix) with ESMTP id F3C7FE5F3F for ; Tue, 9 Jul 2013 13:59:23 -0700 (PDT) Received: by mail-ea0-f176.google.com with SMTP id z15so4209029ead.35 for ; Tue, 09 Jul 2013 13:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=sV48yBTL92FYiQM89SfwUzgMdpozS5OZDnvrvwhyGTM=; b=Fm5daiG9p8TDVO2uhS3YFF05/MQZJXtfsYSbtTsNT8SJVwSJe5FPV9h78Ca7hfPMdr dyR+ufdKXRRxa+rpXq6D7td6M9tddoXtumK6A2jvJThjBlDk0alFZP086buoceOppjIm mpkslFYTfJGdFZizULDyJLAQg50HXiw6J32UI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=sV48yBTL92FYiQM89SfwUzgMdpozS5OZDnvrvwhyGTM=; b=LncTxX8LQZ3eUMB/zF5a+65IN8Pp6hkuQlSSg6FpNHtUo/A7qReo2YcStrAiWdxvJi yJKbLL4u0GofZFNRqslTT6OY4vEGk6LpK2yNS+VxYtNOAkuBcoB3WcUBUIMJ1aiDXP86 Ed8HuIeP0zOAztMsroNL1LVyv45n54YCyxUq+2Nn//OON3lhOoxeL+Y16ZdcXj1kckw1 rrWc3UU4Nw+3liwjV5QWAabNPLLhd1kQmmBaQQVPTPyZcMeq/ReENZrZHxlxl+XZwn41 1YRtUHc8E2c8qe4dDnrgdvlGbzDP6emJqpmAhlayXnzY0VZX2NW3hqzzUzi7eYJNaYcu W2EQ== X-Received: by 10.14.209.197 with SMTP id s45mr32729627eeo.108.1373403563127; Tue, 09 Jul 2013 13:59:23 -0700 (PDT) Received: from natalie.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id l42sm54075155eeo.14.2013.07.09.13.59.21 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 09 Jul 2013 13:59:22 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 9 Jul 2013 22:59:16 +0200 Message-Id: <1373403556-1677-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1372973734-7601-4-git-send-email-daniel.vetter@ffwll.ch> References: <1372973734-7601-4-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkUy2z9KjY2kX1AypuO0mxQVjVZdalmSMvfF3BKZY9MacAR8Ueer1XmXQV4GaEtba9nhver Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: improve GEN7_ERR_INT clearing for fifo underrun reporting X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Same treatment as for SERR_INT: If we clear only the bit for the pipe we're enabling (but unconditionally) then we can always check for possible underruns after having disabled the interrupt. That way pipe underruns won't be lost, but at worst only get reported in a delayed fashion. v2: The same logic bug as in the SERR handling change also existed here. The same bugfix of only reporting missed underruns when the error interrupt was masked applies, too. v3: Do the same fixes as for the SERR handling that Paulo suggested in his review: - s/%i/%c/ fix in the debug output - move the DE_ERR_INT_IVB read into the respective if block Cc: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 20 +++++++++++++------- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index dd9d999..76e977b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -154,21 +154,27 @@ static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, } static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, - bool enable) + enum pipe pipe, bool enable) { struct drm_i915_private *dev_priv = dev->dev_private; - if (enable) { + I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); + if (!ivb_can_enable_err_int(dev)) return; - I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A | - ERR_INT_FIFO_UNDERRUN_B | - ERR_INT_FIFO_UNDERRUN_C); - ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); } else { + bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); + + /* Change the state _after_ we've read out the current one. */ ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); + + if (!was_enabled && + (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { + DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", + pipe_name(pipe)); + } } } @@ -274,7 +280,7 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, if (IS_GEN5(dev) || IS_GEN6(dev)) ironlake_set_fifo_underrun_reporting(dev, pipe, enable); else if (IS_GEN7(dev)) - ivybridge_set_fifo_underrun_reporting(dev, enable); + ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); done: spin_unlock_irqrestore(&dev_priv->irq_lock, flags); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7e2684f..43e81c1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -681,6 +681,7 @@ #define ERR_INT_FIFO_UNDERRUN_C (1<<6) #define ERR_INT_FIFO_UNDERRUN_B (1<<3) #define ERR_INT_FIFO_UNDERRUN_A (1<<0) +#define ERR_INT_FIFO_UNDERRUN(pipe) (1<< (pipe*3)) #define FPGA_DBG 0x42300 #define FPGA_DBG_RM_NOCLAIM (1<<31)