From patchwork Fri Jul 12 20:03:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?St=C3=A9phane_Marchesin?= X-Patchwork-Id: 2827058 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3A5309F756 for ; Fri, 12 Jul 2013 20:04:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 450922012D for ; Fri, 12 Jul 2013 20:04:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 66B0820125 for ; Fri, 12 Jul 2013 20:04:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A0B8436AB for ; Fri, 12 Jul 2013 13:04:01 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f177.google.com (mail-pd0-f177.google.com [209.85.192.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 475DFE6087 for ; Fri, 12 Jul 2013 13:03:51 -0700 (PDT) Received: by mail-pd0-f177.google.com with SMTP id p10so8936558pdj.22 for ; Fri, 12 Jul 2013 13:03:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; bh=MDxP7P4/Ng2UK6/rVDxflGX5BZgk2dudhJNvQxpYvGo=; b=P0tUabETBZu36j8OQh+6D4fWNqTjKx9CU/FsB6S8jzd+hG+GwmbqpiX8ocTSElS/uG LAwbPp1iCbAsrLwdyXfOpEPsKWoYULftoy+iGPUPLaQKWWxKuOIr76PnRMIIoCPRYPwN Y+xnQBkBmJ8Q1Y120yT6ycRtmxFwQsBX/NBSc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding:x-gm-message-state; bh=MDxP7P4/Ng2UK6/rVDxflGX5BZgk2dudhJNvQxpYvGo=; b=Dy6AJHPi6uMa0ED/Zyd4xKcx+1gHafXc+e+338m1GYE/lJrKOpOk88Y+pJzE0QCGBY EnpDvBdLtNCHdWHIjV0HkhBFQMH7JhBsacv/Gf5WGpxEbCeWo08DC+O3DjFfY3B33W99 JLpzZxGwJymrp3PmmJCldW9E0q81JYWlG8fTdH6hru/Fj6Nnx4NLxkLTbHhGatQVcTYt NSKko5R5hznA04wbucrOKTqEDKsSU1Qeb449bV6k/t0AShQxGanGdTmySLC2qOvdnee4 ICiQsnmlDAExBr5oB0DmerQDfXeGjIcJ1JZ4ijvlcCAAHXx9bl+UAS1ZlqcZGlrX8wA2 3aWQ== X-Received: by 10.66.219.1 with SMTP id pk1mr10702123pac.29.1373659431134; Fri, 12 Jul 2013 13:03:51 -0700 (PDT) Received: from localhost ([2620:0:1000:1b01:82c1:6eff:fef8:b068]) by mx.google.com with ESMTPSA id eg3sm49774818pac.1.2013.07.12.13.03.48 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 12 Jul 2013 13:03:49 -0700 (PDT) From: =?UTF-8?q?St=C3=A9phane=20Marchesin?= To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Jul 2013 13:03:46 -0700 Message-Id: <1373659426-18245-1-git-send-email-marcheu@chromium.org> X-Mailer: git-send-email 1.8.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnczqqe4PFwGpPQys6tCvXbDC6kM2vOIygONYc6dCHdqLHveU9GWWdSrazd/Yjox87ayqXz Subject: [Intel-gfx] [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes on eDP. This fixes eDP on hsw with > 2 lanes. Signed-off-by: Stéphane Marchesin Reviewed-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_dp.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 324211a..5e3f97b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1348,7 +1348,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) intel_dig_port->port = port; intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & - DDI_BUF_PORT_REVERSAL; + (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); intel_encoder->type = INTEL_OUTPUT_UNKNOWN; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b739712..a1d838c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -834,10 +834,11 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, * configuration happens (oddly) in ironlake_pch_enable */ - /* Preserve the BIOS-computed detected bit. This is + /* Preserve the BIOS-computed detected and 4 lanes bits. This is * supposed to be read-only. */ - intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; + intel_dp->DP = I915_READ(intel_dp->output_reg) & + (DP_DETECTED | DDI_A_4_LANES); /* Handle DP bits in common between all three register formats */ intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;