From patchwork Fri Jul 26 06:35:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 2833797 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8A6F79F243 for ; Fri, 26 Jul 2013 06:41:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9F00D2012F for ; Fri, 26 Jul 2013 06:41:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9C9352012D for ; Fri, 26 Jul 2013 06:41:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A337E6BAE for ; Thu, 25 Jul 2013 23:41:19 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f46.google.com (mail-ee0-f46.google.com [74.125.83.46]) by gabe.freedesktop.org (Postfix) with ESMTP id C72B3E5FD2 for ; Thu, 25 Jul 2013 23:35:51 -0700 (PDT) Received: by mail-ee0-f46.google.com with SMTP id d41so1351378eek.33 for ; Thu, 25 Jul 2013 23:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=N9Yb4F2ZCOhHb4W27xgF9zoS1VaKT74sROvCYBjtw/c=; b=XUbvoX8x88Z04I4Lw/Ru0YlP/+GcHZ3xX5gGyn02L/9Z4kKBLsJknqCcVqHRvYus3X RUG4DKvSJJ5yaYeUIrMT6Y+bZ9gxCVsjA4zGFpQ8hZujMPZXb2OYM5QtLCHmsvZnqSKL IGMzLNx9Vrnop3I69+Nv4dLSSQa1IfJ6sFqGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=N9Yb4F2ZCOhHb4W27xgF9zoS1VaKT74sROvCYBjtw/c=; b=FLFI8hGW4wMg1F4dvz7wa9HFgxJfa8YSjy3/swhGYWU8LmmmJhvRJ5cDUqxmft/ySh ctmt2BoFg/DlcLgufjlKejSEPb0NUXJMZwIFSNrpOcau2gqAFjwv1EV+FLeL2v9QPkBy YwNgYoSzHPri+w7ZWVxw42bUlnPBkvDiaWVejqdevacy4xULvVaocwW79JvJM30x821M XwGDJAJAweiOojXoxlBTOgbEtZqMgJVyn5fHkq87OnL23Umf7pgyol9ZWNSh+Dj/o+4z hL7pOkGcekwoxA6aY89SgowxwiCMezc1j8q11n4cy9+/vMclH+L1xbwr4tz9k/fKyqr9 pqYw== X-Received: by 10.15.31.9 with SMTP id x9mr45855007eeu.103.1374820550840; Thu, 25 Jul 2013 23:35:50 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id n5sm78791639eed.9.2013.07.25.23.35.49 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 25 Jul 2013 23:35:50 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 26 Jul 2013 08:35:42 +0200 Message-Id: <1374820542-28282-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1374820542-28282-1-git-send-email-daniel.vetter@ffwll.ch> References: <1374820542-28282-1-git-send-email-daniel.vetter@ffwll.ch> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlIuGQDyuhLm1wJ4Kv52DME4xtnZHrlv3nAWcE46AxQpKCUvLynw8gZruwsxWF+E4VP4PFX Cc: Daniel Vetter , Stuart Abercrombie Subject: [Intel-gfx] [PATCH 2/2] drm/i915: fix pnv display core clock readout out X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We need the correct clock to accurately assess whether we need to enable the double wide pipe mode or not. Cc: Chris Wilson Cc: Stéphane Marchesin Cc: Stuart Abercrombie Signed-off-by: Daniel Vetter Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6caa748..3aebe5d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -61,6 +61,12 @@ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) +#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) +#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) +#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) +#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) +#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b3389d7..3e66f05 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) return 200000; } +static int pnv_get_display_clock_speed(struct drm_device *dev) +{ + u16 gcfgc = 0; + + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_267_MHZ_PNV: + return 267000; + case GC_DISPLAY_CLOCK_333_MHZ_PNV: + return 333000; + case GC_DISPLAY_CLOCK_444_MHZ_PNV: + return 444000; + case GC_DISPLAY_CLOCK_200_MHZ_PNV: + return 200000; + default: + DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); + case GC_DISPLAY_CLOCK_133_MHZ_PNV: + return 133000; + case GC_DISPLAY_CLOCK_167_MHZ_PNV: + return 167000; + } +} + static int i915gm_get_display_clock_speed(struct drm_device *dev) { u16 gcfgc = 0; @@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device *dev) else if (IS_I915G(dev)) dev_priv->display.get_display_clock_speed = i915_get_display_clock_speed; - else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) + else if (IS_I945GM(dev) || IS_845G(dev)) dev_priv->display.get_display_clock_speed = i9xx_misc_get_display_clock_speed; + else if (IS_PINEVIEW(dev)) + dev_priv->display.get_display_clock_speed = + pnv_get_display_clock_speed; else if (IS_I915GM(dev)) dev_priv->display.get_display_clock_speed = i915gm_get_display_clock_speed;