From patchwork Wed Aug 28 17:52:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 2850934 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C79CD9F485 for ; Wed, 28 Aug 2013 18:19:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 14EDA2052A for ; Wed, 28 Aug 2013 18:19:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2E98D20525 for ; Wed, 28 Aug 2013 18:19:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CF47E7A9F for ; Wed, 28 Aug 2013 11:19:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f175.google.com (mail-gh0-f175.google.com [209.85.160.175]) by gabe.freedesktop.org (Postfix) with ESMTP id 4DD10E6949 for ; Wed, 28 Aug 2013 10:53:50 -0700 (PDT) Received: by mail-gh0-f175.google.com with SMTP id z19so1613214ghb.6 for ; Wed, 28 Aug 2013 10:53:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=qpCfN66W5+D2R7tsOcz79tWAZdb1ZZdrMHAeSB3zykw=; b=YdFK1zQsQ+85C7CB8FkAIxTAUAf9NepqOwd1ZxXw1Jw95oAB7mzrYWa8f4AXYfp70N irLfKSlR4Kth8HGMVSqwB6xNbG28RDusvCGLcYIf4lLk5WCzm0sK2oASocLwSFMsTrR/ lBCuZYHgxe/5qHXajT3RVH5x/dZnY+kTqV+Z0uG5atHFTAIoBWIcDpVTDOIb4dxM5x6A 4gAsi2aq3rM0SC3YCB+wIKt9bw80IuDP8TWX0yV8S//XOAz+DrXfbmbfjDmH5kXflXAh bfaHjdnDUfDTlDEBk5K/EMPf2o6cN36qYi1CR18A8z2Pu2Q6kGOWuM85rJApkAOG8w3f qgBw== X-Received: by 10.236.158.100 with SMTP id p64mr38525yhk.148.1377712429651; Wed, 28 Aug 2013 10:53:49 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPSA id e65sm32983040yhc.18.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 28 Aug 2013 10:53:48 -0700 (PDT) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Wed, 28 Aug 2013 14:52:58 -0300 Message-Id: <1377712378-2943-1-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.8.1.4 Subject: [Intel-gfx] [PATCH] drm/i915: Introduce HSW GT Slice Shutdown on Boot. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Slice shutdown is a power savings feature whereby parts of HW i.e. slice is shut off on boot or dynamically to save power. This patch only introduces a way to disable half of Haswell slices on boot. Dynamic shutdown is yet to be implemented. This gt_init already sets MI_PREDICATE_RESULT_2 appropriately. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 735dd56..fe89bdc 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -154,6 +154,11 @@ module_param_named(prefault_disable, i915_prefault_disable, bool, 0600); MODULE_PARM_DESC(prefault_disable, "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); +int i915_slice_shutdown __read_mostly = 0; +module_param_named(slice_shutdown, i915_slice_shutdown, int, 0600); +MODULE_PARM_DESC(slice_shutdown, + "Disable half of EUs at boot time to save power."); + static struct drm_driver driver; extern int intel_agp_enabled; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 05de1ca..796aac7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1595,6 +1595,8 @@ struct drm_i915_file_private { ((dev)->pci_device & 0xFF00) == 0x0C00) #define IS_ULT(dev) (IS_HASWELL(dev) && \ ((dev)->pci_device & 0xFF00) == 0x0A00) +#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ + ((dev)->pci_device & 0x00F0) == 0x0020) /* * The genX designation typically refers to the render engine, so render @@ -1712,6 +1714,7 @@ extern bool i915_fastboot __read_mostly; extern int i915_enable_pc8 __read_mostly; extern int i915_pc8_timeout __read_mostly; extern bool i915_prefault_disable __read_mostly; +extern int i915_slice_shutdown __read_mostly; extern int i915_suspend(struct drm_device *dev, pm_message_t state); extern int i915_resume(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8b81516..9ca93c4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -278,6 +278,22 @@ #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ #define MI_SEMAPHORE_SYNC_INVALID (3<<16) + +#define MI_PREDICATE_RESULT_2 (0x2214) +#define LOWER_SLICE_ENABLED (1<<0) +#define LOWER_SLICE_DISABLED (0<<0) + +#define HSW_GT_SLICE_INFO 0x138064 +#define SLICE_SEL_BOTH (1<<3) +#define SLICE_AUTOWAKE (1<<2) +#define SLICE_STATUS_MASK 0x3 +#define SLICE_STATUS_GT_OFF (0<<0) +#define SLICE_STATUS_MAIN_ON (2<<0) +#define SLICE_STATUS_BOTH_ON (3<<0) + +#define HSW_SLICESHUTDOWN 0xA190 +#define SLICE_SHUTDOWN (1<<0) + /* * 3D instructions used by the kernel */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6b1d003..4301401 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3617,6 +3617,28 @@ static void gen6_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv); } +static void intel_init_gt_slices(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!IS_HSW_GT3(dev)) + return; + + if (i915_slice_shutdown) { + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); + + I915_WRITE(HSW_SLICESHUTDOWN, SLICE_SHUTDOWN); + POSTING_READ(HSW_SLICESHUTDOWN); + + I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH); + POSTING_READ(HSW_GT_SLICE_INFO); + } else { + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + POSTING_READ(MI_PREDICATE_RESULT_2); + } +} + void gen6_update_ring_freq(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4630,6 +4652,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) } else { gen6_enable_rps(dev); gen6_update_ring_freq(dev); + intel_init_gt_slices(dev); } mutex_unlock(&dev_priv->rps.hw_lock); }