| Message ID | 1377719146-4337-1-git-send-email-rodrigo.vivi@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Aug 28, 2013 at 04:45:46PM -0300, Rodrigo Vivi wrote: > Batchbuffers constructed by userspace can conditionalise their URB > allocations through the use of the MI_SET_PREDICATE command. This > command can read the MI_PREDICATE_RESULT_2 register to see how many > slices are enabled on GT3, and by virtue of the result, scale their > memory allocations to fit enabled memory. > > Of course, this only works if the kernel sets the appropriate bit in the > register first. > > v2: Better commit subject and message by Chris Wilson. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Credits-by: Yejun Guo <yejun.guo@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> I would have written the I915_WRITE() differently but, Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
On Wed, Aug 28, 2013 at 10:09:40PM +0100, Chris Wilson wrote: > On Wed, Aug 28, 2013 at 04:45:46PM -0300, Rodrigo Vivi wrote: > > Batchbuffers constructed by userspace can conditionalise their URB > > allocations through the use of the MI_SET_PREDICATE command. This > > command can read the MI_PREDICATE_RESULT_2 register to see how many > > slices are enabled on GT3, and by virtue of the result, scale their > > memory allocations to fit enabled memory. > > > > Of course, this only works if the kernel sets the appropriate bit in the > > register first. > > > > v2: Better commit subject and message by Chris Wilson. > > > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Credits-by: Yejun Guo <yejun.guo@intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> > > I would have written the I915_WRITE() differently but, > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 14299a4..9e25079 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1519,6 +1519,8 @@ struct drm_i915_file_private { ((dev)->pci_device & 0xFF00) == 0x0C00) #define IS_ULT(dev) (IS_HASWELL(dev) && \ ((dev)->pci_device & 0xFF00) == 0x0A00) +#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ + ((dev)->pci_device & 0x00F0) == 0x0020) /* * The genX designation typically refers to the render engine, so render diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f705314..d88c8cb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4328,6 +4328,11 @@ i915_gem_init_hw(struct drm_device *dev) if (dev_priv->ellc_size) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); + if (IS_HSW_GT3(dev)) + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); + else + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); + if (HAS_PCH_NOP(dev)) { u32 temp = I915_READ(GEN7_MSG_CTL); temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 53d0e70..2ab0de6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -278,6 +278,11 @@ #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ #define MI_SEMAPHORE_SYNC_INVALID (3<<16) + +#define MI_PREDICATE_RESULT_2 (0x2214) +#define LOWER_SLICE_ENABLED (1<<0) +#define LOWER_SLICE_DISABLED (0<<0) + /* * 3D instructions used by the kernel */
Batchbuffers constructed by userspace can conditionalise their URB allocations through the use of the MI_SET_PREDICATE command. This command can read the MI_PREDICATE_RESULT_2 register to see how many slices are enabled on GT3, and by virtue of the result, scale their memory allocations to fit enabled memory. Of course, this only works if the kernel sets the appropriate bit in the register first. v2: Better commit subject and message by Chris Wilson. Cc: Chris Wilson <chris@chris-wilson.co.uk> Credits-by: Yejun Guo <yejun.guo@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 5 +++++ drivers/gpu/drm/i915/i915_reg.h | 5 +++++ 3 files changed, 12 insertions(+)