diff mbox

[11/19] drm/i915: Don't compute 5/6 DDB split w/ zero active pipes

Message ID 1377862239-17052-12-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Aug. 30, 2013, 11:30 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When there are zero active pipes, all the watermarks should be zero
also. No point in wasting time w/ computing the 5/6 split watermark
config.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5c5fba4..7b4f7d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2881,7 +2881,7 @@  static void haswell_update_wm(struct drm_crtc *crtc)
 	ilk_wm_merge(dev, &max, &lp_wm_1_2);
 
 	/* 5/6 split only in single pipe config on IVB+ */
-	if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1) {
+	if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active == 1) {
 		ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
 		ilk_wm_merge(dev, &max, &lp_wm_5_6);