From patchwork Fri Aug 30 11:30:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 2851916 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F2EEF9F2F4 for ; Fri, 30 Aug 2013 11:42:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF5B12031C for ; Fri, 30 Aug 2013 11:42:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C482F2034D for ; Fri, 30 Aug 2013 11:42:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BAEDA436D3 for ; Fri, 30 Aug 2013 04:42:35 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id DC63BE7D4F for ; Fri, 30 Aug 2013 04:31:26 -0700 (PDT) Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga101.ch.intel.com with ESMTP; 30 Aug 2013 04:31:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.89,990,1367996400"; d="scan'208";a="288868981" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.168]) by AZSMGA002.ch.intel.com with SMTP; 30 Aug 2013 04:31:08 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 30 Aug 2013 14:31:07 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Aug 2013 14:30:28 +0300 Message-Id: <1377862239-17052-9-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1377862239-17052-1-git-send-email-ville.syrjala@linux.intel.com> References: <1377862239-17052-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/19] drm/i915: Move LP1+ watermark merging out from hsw_compute_wm_results() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä I want to convert hsw_find_best_result() to use intel_pipe_wm, so we need to move the merging to happen outside hsw_compute_wm_results(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1fb904a..b538d09 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2697,26 +2697,23 @@ static void ilk_wm_merge(struct drm_device *dev, } static void hsw_compute_wm_results(struct drm_device *dev, - const struct hsw_wm_maximums *lp_maximums, + const struct intel_pipe_wm *lp_wm, struct hsw_wm_values *results) { struct intel_crtc *intel_crtc; int level, wm_lp; - struct intel_pipe_wm lp_wm = {}; - - ilk_wm_merge(dev, lp_maximums, &lp_wm); memset(results, 0, sizeof(*results)); - results->enable_fbc_wm = lp_wm.fbc_wm_enabled; + results->enable_fbc_wm = lp_wm->fbc_wm_enabled; /* LP1+ register values */ for (wm_lp = 1; wm_lp <= 3; wm_lp++) { const struct intel_wm_level *r; - level = wm_lp + (wm_lp >= 2 && lp_wm.wm[4].enable); + level = wm_lp + (wm_lp >= 2 && lp_wm->wm[4].enable); - r = &lp_wm.wm[level]; + r = &lp_wm->wm[level]; if (!r->enable) break; @@ -2878,6 +2875,7 @@ static void haswell_update_wm(struct drm_crtc *crtc) struct hsw_wm_values results_1_2, results_5_6, *best_results; enum intel_ddb_partitioning partitioning; struct intel_pipe_wm pipe_wm = {}; + struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}; hsw_compute_wm_parameters(crtc, ¶ms, &lp_max_1_2, &lp_max_5_6); @@ -2888,9 +2886,12 @@ static void haswell_update_wm(struct drm_crtc *crtc) intel_crtc->wm.active = pipe_wm; - hsw_compute_wm_results(dev, &lp_max_1_2, &results_1_2); + ilk_wm_merge(dev, &lp_max_1_2, &lp_wm_1_2); + ilk_wm_merge(dev, &lp_max_5_6, &lp_wm_5_6); + + hsw_compute_wm_results(dev, &lp_wm_1_2, &results_1_2); if (lp_max_1_2.pri != lp_max_5_6.pri) { - hsw_compute_wm_results(dev, &lp_max_5_6, &results_5_6); + hsw_compute_wm_results(dev, &lp_wm_5_6, &results_5_6); best_results = hsw_find_best_result(&results_1_2, &results_5_6); } else { best_results = &results_1_2;