From patchwork Fri Aug 30 17:57:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chon Ming Lee X-Patchwork-Id: 2851804 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A8A0B9F313 for ; Fri, 30 Aug 2013 05:54:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C5376202B9 for ; Fri, 30 Aug 2013 05:54:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 99143202B8 for ; Fri, 30 Aug 2013 05:54:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B47B43699 for ; Thu, 29 Aug 2013 22:54:30 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E38BE6BA9 for ; Thu, 29 Aug 2013 22:54:07 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 29 Aug 2013 22:54:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.89,989,1367996400"; d="scan'208";a="394368864" Received: from clee30-sandy.png.intel.com ([172.30.66.53]) by fmsmga002.fm.intel.com with ESMTP; 29 Aug 2013 22:54:05 -0700 From: Chon Ming Lee To: intel-gfx@lists.freedesktop.org Date: Sat, 31 Aug 2013 01:57:44 +0800 Message-Id: <1377885465-23851-1-git-send-email-chon.ming.lee@intel.com> X-Mailer: git-send-email 1.7.7.6 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Modify DP set clock to accomodate more eDP timings. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP eDP 1.4 supports 4-5 extra link rates in additional to current 2 link rate. Create a structure to store the DPLL divisor data to improve readability. Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/intel_dp.c | 48 +++++++++++++++++++------------------- 1 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2151d13..ab8a5ff 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -38,6 +38,19 @@ #define DP_LINK_CHECK_TIMEOUT (10 * 1000) +struct dp_link_dpll{ + int link_bw; + struct dpll dpll; +}; + +static const struct dp_link_dpll gen4_dpll[] = + {{ DP_LINK_BW_1_62, {2,23,8,2,10,0,0,0,0}}, + { DP_LINK_BW_2_7, {1,14,2,1,10,0,0,0,0}}}; + +static const struct dp_link_dpll pch_dpll[] = + {{ DP_LINK_BW_1_62, {1,12,9,2,10,0,0,0,0}}, + { DP_LINK_BW_2_7, {2,14,8,1,10,0,0,0,0}}}; + /** * is_edp - is the given port attached to an eDP panel (either CPU or PCH) * @intel_dp: DP struct @@ -649,37 +662,24 @@ intel_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config, int link_bw) { struct drm_device *dev = encoder->base.dev; + int i; if (IS_G4X(dev)) { - if (link_bw == DP_LINK_BW_1_62) { - pipe_config->dpll.p1 = 2; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.n = 2; - pipe_config->dpll.m1 = 23; - pipe_config->dpll.m2 = 8; - } else { - pipe_config->dpll.p1 = 1; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.n = 1; - pipe_config->dpll.m1 = 14; - pipe_config->dpll.m2 = 2; + for(i = 0; i < sizeof(gen4_dpll) / sizeof(struct dp_link_dpll); i++) { + if (link_bw == gen4_dpll[i].link_bw){ + pipe_config->dpll = gen4_dpll[i].dpll; + break; + } } pipe_config->clock_set = true; } else if (IS_HASWELL(dev)) { /* Haswell has special-purpose DP DDI clocks. */ } else if (HAS_PCH_SPLIT(dev)) { - if (link_bw == DP_LINK_BW_1_62) { - pipe_config->dpll.n = 1; - pipe_config->dpll.p1 = 2; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.m1 = 12; - pipe_config->dpll.m2 = 9; - } else { - pipe_config->dpll.n = 2; - pipe_config->dpll.p1 = 1; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.m1 = 14; - pipe_config->dpll.m2 = 8; + for(i = 0; i < sizeof(pch_dpll) / sizeof(struct dp_link_dpll); i++) { + if (link_bw == pch_dpll[i].link_bw){ + pipe_config->dpll = pch_dpll[i].dpll; + break; + } } pipe_config->clock_set = true; } else if (IS_VALLEYVIEW(dev)) {