From patchwork Fri Aug 30 17:57:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chon Ming Lee X-Patchwork-Id: 2851805 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 123069F313 for ; Fri, 30 Aug 2013 05:55:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 261C72012B for ; Fri, 30 Aug 2013 05:55:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0F0B720127 for ; Fri, 30 Aug 2013 05:55:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04808E6BA9 for ; Thu, 29 Aug 2013 22:55:25 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 481F843685 for ; Thu, 29 Aug 2013 22:54:08 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 29 Aug 2013 22:54:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.89,989,1367996400"; d="scan'208";a="394368875" Received: from clee30-sandy.png.intel.com ([172.30.66.53]) by fmsmga002.fm.intel.com with ESMTP; 29 Aug 2013 22:54:06 -0700 From: Chon Ming Lee To: intel-gfx@lists.freedesktop.org Date: Sat, 31 Aug 2013 01:57:45 +0800 Message-Id: <1377885465-23851-2-git-send-email-chon.ming.lee@intel.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1377885465-23851-1-git-send-email-chon.ming.lee@intel.com> References: <1377885465-23851-1-git-send-email-chon.ming.lee@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For DP pll settings, there is only two golden configs. Instead of running through the algorithm to determine it, hardcode the value and get it determine in intel_dp_set_clock. Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/intel_display.c | 22 ++++------------------ drivers/gpu/drm/i915/intel_dp.c | 12 +++++++++++- 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f526ea9..453fa16 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -339,19 +339,6 @@ static const intel_limit_t intel_limits_vlv_hdmi = { .p2_slow = 2, .p2_fast = 20 }, }; -static const intel_limit_t intel_limits_vlv_dp = { - .dot = { .min = 25000, .max = 270000 }, - .vco = { .min = 4000000, .max = 6000000 }, - .n = { .min = 1, .max = 7 }, - .m = { .min = 22, .max = 450 }, - .m1 = { .min = 2, .max = 3 }, - .m2 = { .min = 11, .max = 156 }, - .p = { .min = 10, .max = 30 }, - .p1 = { .min = 1, .max = 3 }, - .p2 = { .dot_limit = 270000, - .p2_slow = 2, .p2_fast = 20 }, -}; - static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, int refclk) { @@ -414,10 +401,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) } else if (IS_VALLEYVIEW(dev)) { if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) limit = &intel_limits_vlv_dac; - else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) + else limit = &intel_limits_vlv_hdmi; - else - limit = &intel_limits_vlv_dp; } else if (!IS_GEN2(dev)) { if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) limit = &intel_limits_i9xx_lvds; @@ -4889,15 +4874,16 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, } refclk = i9xx_get_refclk(crtc, num_connectors); + + limit = intel_limit(crtc, refclk); - if (!is_dsi) { + if (!is_dsi && !intel_crtc->config.clock_set) { /* * Returns a set of divisors for the desired target clock with * the given refclk, or FALSE. The returned values represent * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + * 2) / p1 / p2. */ - limit = intel_limit(crtc, refclk); ok = dev_priv->display.find_dpll(limit, crtc, intel_crtc->config.port_clock, refclk, NULL, &clock); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ab8a5ff..89a2606 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -51,6 +51,10 @@ static const struct dp_link_dpll pch_dpll[] = {{ DP_LINK_BW_1_62, {1,12,9,2,10,0,0,0,0}}, { DP_LINK_BW_2_7, {2,14,8,1,10,0,0,0,0}}}; +static const struct dp_link_dpll vlv_dpll[] = + {{ DP_LINK_BW_1_62, {5,3,81,3,2,0,0,0,0}}, + { DP_LINK_BW_2_7, {1,2,27,2,2,0,0,0,0}}}; + /** * is_edp - is the given port attached to an eDP panel (either CPU or PCH) * @intel_dp: DP struct @@ -683,7 +687,13 @@ intel_dp_set_clock(struct intel_encoder *encoder, } pipe_config->clock_set = true; } else if (IS_VALLEYVIEW(dev)) { - /* FIXME: Need to figure out optimized DP clocks for vlv. */ + for(i = 0; i < sizeof(vlv_dpll) / sizeof(struct dp_link_dpll); i++) { + if (link_bw == vlv_dpll[i].link_bw){ + pipe_config->dpll = vlv_dpll[i].dpll; + break; + } + } + pipe_config->clock_set = true; } }