From patchwork Tue Sep 3 17:30:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chon Ming Lee X-Patchwork-Id: 2853052 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 513689F499 for ; Tue, 3 Sep 2013 05:30:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 64BAF201EA for ; Tue, 3 Sep 2013 05:30:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F1514201B4 for ; Tue, 3 Sep 2013 05:30:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05B74E5D42 for ; Mon, 2 Sep 2013 22:30:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B5B3E5C1A for ; Mon, 2 Sep 2013 22:26:51 -0700 (PDT) Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga101.ch.intel.com with ESMTP; 02 Sep 2013 22:26:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.89,1011,1367996400"; d="scan'208"; a="290058323" Received: from clee30-sandy.png.intel.com ([172.30.66.53]) by AZSMGA002.ch.intel.com with ESMTP; 02 Sep 2013 22:26:48 -0700 From: Chon Ming Lee To: intel-gfx@lists.freedesktop.org Date: Wed, 4 Sep 2013 01:30:37 +0800 Message-Id: <1378229438-29178-1-git-send-email-chon.ming.lee@intel.com> X-Mailer: git-send-email 1.7.7.6 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Modify DP set clock to accomodate more eDP timings v2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP eDP 1.4 supports 4-5 extra link rates in additional to current 2 link rate. Create a structure to store the DPLL divisor data to improve readability. v2: Fix the gen4_dpll/pch_dpll initialization to C99 designated initializers, and use a single loop for all platforms. (Jani and Daniel) Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/intel_dp.c | 65 ++++++++++++++++++++++----------------- 1 files changed, 37 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2151d13..fd09058 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -38,6 +38,27 @@ #define DP_LINK_CHECK_TIMEOUT (10 * 1000) +struct dp_link_dpll { + int link_bw; + struct dpll dpll; +}; + +static const struct dp_link_dpll gen4_dpll[] = +{ + { DP_LINK_BW_1_62, + { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 }}, + { DP_LINK_BW_2_7, + { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 }} +}; + +static const struct dp_link_dpll pch_dpll[] = +{ + { DP_LINK_BW_1_62, + { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 }}, + { DP_LINK_BW_2_7, + { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 }} +}; + /** * is_edp - is the given port attached to an eDP panel (either CPU or PCH) * @intel_dp: DP struct @@ -649,42 +670,30 @@ intel_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config, int link_bw) { struct drm_device *dev = encoder->base.dev; + const struct dp_link_dpll *divisor = NULL; + int i, count = 0; if (IS_G4X(dev)) { - if (link_bw == DP_LINK_BW_1_62) { - pipe_config->dpll.p1 = 2; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.n = 2; - pipe_config->dpll.m1 = 23; - pipe_config->dpll.m2 = 8; - } else { - pipe_config->dpll.p1 = 1; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.n = 1; - pipe_config->dpll.m1 = 14; - pipe_config->dpll.m2 = 2; - } - pipe_config->clock_set = true; + divisor = gen4_dpll; + count = ARRAY_SIZE(gen4_dpll); } else if (IS_HASWELL(dev)) { /* Haswell has special-purpose DP DDI clocks. */ } else if (HAS_PCH_SPLIT(dev)) { - if (link_bw == DP_LINK_BW_1_62) { - pipe_config->dpll.n = 1; - pipe_config->dpll.p1 = 2; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.m1 = 12; - pipe_config->dpll.m2 = 9; - } else { - pipe_config->dpll.n = 2; - pipe_config->dpll.p1 = 1; - pipe_config->dpll.p2 = 10; - pipe_config->dpll.m1 = 14; - pipe_config->dpll.m2 = 8; - } - pipe_config->clock_set = true; + divisor = pch_dpll; + count = ARRAY_SIZE(pch_dpll); } else if (IS_VALLEYVIEW(dev)) { /* FIXME: Need to figure out optimized DP clocks for vlv. */ } + + if (divisor && count) { + for (i = 0; i < count; i++) { + if (link_bw == divisor[i].link_bw) { + pipe_config->dpll = divisor[i].dpll; + pipe_config->clock_set = true; + break; + } + } + } } bool