From patchwork Wed Sep 4 15:30:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 2853782 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A80869F485 for ; Wed, 4 Sep 2013 15:36:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8175D20166 for ; Wed, 4 Sep 2013 15:36:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id DA6A12015E for ; Wed, 4 Sep 2013 15:36:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 997EBE70D5 for ; Wed, 4 Sep 2013 08:36:27 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B697E6858 for ; Wed, 4 Sep 2013 08:30:21 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 04 Sep 2013 08:27:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.89,1021,1367996400"; d="scan'208"; a="398123033" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.167]) by orsmga002.jf.intel.com with SMTP; 04 Sep 2013 08:30:19 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 04 Sep 2013 18:30:18 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 4 Sep 2013 18:30:04 +0300 Message-Id: <1378308607-22046-4-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1378308607-22046-1-git-send-email-ville.syrjala@linux.intel.com> References: <1378308607-22046-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Check pixel clock limits on pre-gen4 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä We don't want to try to push the hardware beyond it's capabilities, so check the pixel clock against the display core clock limit. Do it for pre-gen4 for now since that's where we alread have the double wide pixel clock limit check. Let's assume that when double wide mode is enabled the max pixel clock limit is also doubled. FIXME: panel fitter downscaling probably affects the limit on non-pch platforms too, so we'd need another version of ilk_pipe_pixel_rate() to figure that out. FIXME: should check the limits on all platforms. Also sprites affect the max allowed pixel rate on some platforms, so we need to eventually tie all the planes and pipes into one check in the future. But we need plane state pre-compute before that can happen. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7abf31b..9c57a83 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4121,6 +4121,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; + /* FIXME should check pixel clock limits on all platforms */ if (INTEL_INFO(dev)->gen < 4) { struct drm_i915_private *dev_priv = dev->dev_private; int clock_limit = @@ -4134,8 +4135,13 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, * the only reason for the pipe == PIPE_A check? */ if (crtc->pipe == PIPE_A && - adjusted_mode->clock > clock_limit * 9 / 10) + adjusted_mode->clock > clock_limit * 9 / 10) { + clock_limit *= 2; pipe_config->double_wide = true; + } + + if (adjusted_mode->clock > clock_limit * 9 / 10) + return -EINVAL; } /* Cantiga+ cannot handle modes with a hsync front porch of 0.