From patchwork Fri Sep 13 03:59:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chon Ming Lee X-Patchwork-Id: 2878971 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1CDB19F1C0 for ; Thu, 12 Sep 2013 15:56:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D5C4A2020F for ; Thu, 12 Sep 2013 15:56:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 62C33201B6 for ; Thu, 12 Sep 2013 15:56:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 58864E66E6 for ; Thu, 12 Sep 2013 08:56:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 4724FE638D for ; Thu, 12 Sep 2013 08:56:13 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 12 Sep 2013 08:56:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.90,891,1371106800"; d="scan'208";a="359591142" Received: from clee30-sandy.png.intel.com ([172.30.66.91]) by azsmga001.ch.intel.com with ESMTP; 12 Sep 2013 08:56:11 -0700 From: Chon Ming Lee To: intel-gfx@lists.freedesktop.org Date: Fri, 13 Sep 2013 11:59:45 +0800 Message-Id: <1379044785-13193-1-git-send-email-chon.ming.lee@intel.com> X-Mailer: git-send-email 1.7.7.6 Subject: [Intel-gfx] [PATCH] drm/i915: Enable VLV to work in BIOS-less system X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_12_24, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In non PC system, such as IVI, may not use BIOS, instead it uses boot loader with only minimal system initialization. Most of the time, boot loader doesn't come with VBIOS, and depends on device driver to fully initialize the display controller and GPU. For Valleyview, without VBIOS, i915 fails to work. The patch add some missing init code, such as doing a DPIO CMNRESET and program the GMBUS frequency. Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/i915_reg.h | 8 +++++ drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bcee89b..8ddf58a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -382,6 +382,8 @@ #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 /* vlv2 north clock has */ +#define CCK_FUSE_REG 0x8 +#define CCK_FUSE_HPLL_FREQ_MASK 0x3 #define CCK_REG_DSI_PLL_FUSE 0x44 #define CCK_REG_DSI_PLL_CONTROL 0x48 #define DSI_PLL_VCO_EN (1 << 31) @@ -1424,6 +1426,12 @@ #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) +#define CZCLK_CDCLK_FREQ_RATIO (dev_priv->info->display_mmio_offset + 0x6508) +#define CDCLK_FREQ_SHIFT 4 +#define CDCLK_FREQ_MASK 0x1f +#define CZCLK_FREQ_MASK 0xf +#define GMBUS_FREQ (dev_priv->info->display_mmio_offset + 0x6510) + /* * Palette regs */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3c0e0cf..9ef1d28 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9497,6 +9497,31 @@ static bool has_edp_a(struct drm_device *dev) return true; } +static void gmbus_set_freq(struct drm_i915_private *dev_priv, u32 hpll_freq) +{ + int cdclk_ratio[] = { 10, 15, 20, 25, 30, 0, 40, 45, 50, 0, + 60, 0, 0, 75, 80, 0, 90, 0, 100, 0, + 0, 0, 120, 0, 0, 0, 0, 0, 150, 0, 160 }; + int vco_freq[] = { 800, 1600, 2000, 2400 }; + int gmbus_freq = 0, cdclk; + u32 reg_val; + + BUG_ON(hpll_freq > ARRAY_SIZE(vco_freq)); + + reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO); + + cdclk = ((reg_val >> CDCLK_FREQ_SHIFT) & CDCLK_FREQ_MASK) - 1; + + if (cdclk_ratio[cdclk]) + gmbus_freq = vco_freq[hpll_freq] / cdclk_ratio[cdclk] * 10; + + WARN_ON(gmbus_freq == 0); + + if (gmbus_freq != 0) + I915_WRITE(GMBUS_FREQ, gmbus_freq); + +} + static void intel_setup_outputs(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -9555,6 +9580,32 @@ static void intel_setup_outputs(struct drm_device *dev) if (I915_READ(PCH_DP_D) & DP_DETECTED) intel_dp_init(dev, PCH_DP_D, PORT_D); } else if (IS_VALLEYVIEW(dev)) { + u32 reg_val; + + /* Trigger DPIO CMN RESET, require especially in BIOS less + * system + */ + reg_val = I915_READ(DPIO_CTL); + if (!(reg_val & 0x1)) { + I915_WRITE(DPIO_CTL, 0x0); + I915_WRITE(DPIO_CTL, 0x1); + POSTING_READ(DPIO_CTL); + } + + /* In BIOS-less system, program the correct gmbus frequency + * before reading edid. + */ + + /* Obtain SKU information to determine the correct CDCLK */ + mutex_lock(&dev_priv->dpio_lock); + reg_val = vlv_cck_read(dev_priv, CCK_FUSE_REG); + mutex_unlock(&dev_priv->dpio_lock); + + reg_val &= CCK_FUSE_HPLL_FREQ_MASK; + + /* Write CDCLK to GMBUS freq for GMBUS clk generation. */ + gmbus_set_freq(dev_priv, reg_val); + /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,