| Message ID | 1379054361-26440-2-git-send-email-chon.ming.lee@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Sep 13, 2013 at 02:39:20PM +0800, Chon Ming Lee wrote: > Without the DPIO cmnreset, the PLL fail to lock. This should have > done by BIOS. > > v2: Move this to intel_uncore_sanitize to allow it to get call during > resume path. (Daniel) > > Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> > --- > drivers/gpu/drm/i915/intel_uncore.c | 15 +++++++++++++++ > 1 files changed, 15 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 8649f1c..b1f53f3 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -276,10 +276,25 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev) > > void intel_uncore_sanitize(struct drm_device *dev) > { > + struct drm_i915_private *dev_priv = dev->dev_private; > + u32 reg_val; > + > intel_uncore_forcewake_reset(dev); > > /* BIOS often leaves RC6 enabled, but disable it for hw init */ > intel_disable_gt_powersave(dev); > + > + /* Trigger DPIO CMN RESET, require especially in BIOS less > + * system > + */ > + if (IS_VALLEYVIEW(dev)) { > + reg_val = I915_READ(DPIO_CTL); > + if (!(reg_val & 0x1)) { > + I915_WRITE(DPIO_CTL, 0x0); The relevant bit is already 0. Does this write do something useful? I get the impression it just directly controls the cmnreset line, so if it's already 0 the reset is already asserted and rewriting w/ 0 does nothing. Also we have a name for the bit in i915_reg.h, so might as well use it. The spec makes one mention that we could assert cmnreset again after all DPLL and lanes are unused, but in another place it explcitly says we shouldn't touch it after the initial setup. I guess we just have to trust that not touching more than once is the right option. And BTW this is also step 6 in the enable sequence. Don't you need the earlier steps (some clock setup stuff from the looks of it)? > + I915_WRITE(DPIO_CTL, 0x1); > + POSTING_READ(DPIO_CTL); > + } > + } > } > > /* > -- > 1.7.7.6 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8649f1c..b1f53f3 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -276,10 +276,25 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev) void intel_uncore_sanitize(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; + u32 reg_val; + intel_uncore_forcewake_reset(dev); /* BIOS often leaves RC6 enabled, but disable it for hw init */ intel_disable_gt_powersave(dev); + + /* Trigger DPIO CMN RESET, require especially in BIOS less + * system + */ + if (IS_VALLEYVIEW(dev)) { + reg_val = I915_READ(DPIO_CTL); + if (!(reg_val & 0x1)) { + I915_WRITE(DPIO_CTL, 0x0); + I915_WRITE(DPIO_CTL, 0x1); + POSTING_READ(DPIO_CTL); + } + } } /*
Without the DPIO cmnreset, the PLL fail to lock. This should have done by BIOS. v2: Move this to intel_uncore_sanitize to allow it to get call during resume path. (Daniel) Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-)