From patchwork Fri Sep 13 06:39:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chon Ming Lee X-Patchwork-Id: 2881851 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A7587BFF05 for ; Fri, 13 Sep 2013 06:42:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AFF99203F1 for ; Fri, 13 Sep 2013 06:42:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D1E2620383 for ; Fri, 13 Sep 2013 06:42:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9AEBBE67B4 for ; Thu, 12 Sep 2013 23:42:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 97058E653E for ; Thu, 12 Sep 2013 23:41:30 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 12 Sep 2013 23:38:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.90,896,1371106800"; d="scan'208";a="402717125" Received: from clee30-sandy.png.intel.com ([172.30.66.91]) by orsmga002.jf.intel.com with ESMTP; 12 Sep 2013 23:41:29 -0700 From: Chon Ming Lee To: intel-gfx@lists.freedesktop.org Date: Fri, 13 Sep 2013 14:39:21 +0800 Message-Id: <1379054361-26440-3-git-send-email-chon.ming.lee@intel.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1379054361-26440-1-git-send-email-chon.ming.lee@intel.com> References: <[PATCH] drm/i915: Enable VLV to work in BIOS-less system> <1379054361-26440-1-git-send-email-chon.ming.lee@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Program GMBUS Frequency based on the CDCLK X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CDCLK is used to generate the gmbus clock. This is normally done by BIOS. This is only for valleyview platform. v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency during resume. (Daniel) Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/i915_reg.h | 8 +++++++ drivers/gpu/drm/i915/intel_i2c.c | 43 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bcee89b..8ddf58a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -382,6 +382,8 @@ #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 /* vlv2 north clock has */ +#define CCK_FUSE_REG 0x8 +#define CCK_FUSE_HPLL_FREQ_MASK 0x3 #define CCK_REG_DSI_PLL_FUSE 0x44 #define CCK_REG_DSI_PLL_CONTROL 0x48 #define DSI_PLL_VCO_EN (1 << 31) @@ -1424,6 +1426,12 @@ #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) +#define CZCLK_CDCLK_FREQ_RATIO (dev_priv->info->display_mmio_offset + 0x6508) +#define CDCLK_FREQ_SHIFT 4 +#define CDCLK_FREQ_MASK 0x1f +#define CZCLK_FREQ_MASK 0xf +#define GMBUS_FREQ (dev_priv->info->display_mmio_offset + 0x6510) + /* * Palette regs */ diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index d1c1e0f7..a8c4165 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -58,10 +58,53 @@ to_intel_gmbus(struct i2c_adapter *i2c) return container_of(i2c, struct intel_gmbus, adapter); } +static void gmbus_set_freq(struct drm_i915_private *dev_priv) +{ + int cdclk_ratio[] = { 10, 15, 20, 25, 30, 0, 40, 45, 50, 0, + 60, 0, 0, 75, 80, 0, 90, 0, 100, 0, + 0, 0, 120, 0, 0, 0, 0, 0, 150, 0, 160 }; + int vco_freq[] = { 800, 1600, 2000, 2400 }; + int gmbus_freq = 0, cdclk, hpll_freq; + u32 reg_val; + + BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); + + /* Obtain SKU information to determine the correct CDCLK */ + mutex_lock(&dev_priv->dpio_lock); + reg_val = vlv_cck_read(dev_priv, CCK_FUSE_REG); + mutex_unlock(&dev_priv->dpio_lock); + + hpll_freq = reg_val & CCK_FUSE_HPLL_FREQ_MASK; + + /* Get the CDCLK frequency */ + reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO); + + cdclk = ((reg_val >> CDCLK_FREQ_SHIFT) & CDCLK_FREQ_MASK) - 1; + + /* To enable hotplug detect, the gmbus frequency need to set as + * cdclk/1.01 + */ + if (cdclk_ratio[cdclk]) + gmbus_freq = vco_freq[hpll_freq] / cdclk_ratio[cdclk] * 101 / 10; + + WARN_ON(gmbus_freq == 0); + + if (gmbus_freq != 0) + I915_WRITE(GMBUS_FREQ, gmbus_freq); + +} + void intel_i2c_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + + /* In BIOS-less system, program the correct gmbus frequency + * before reading edid. + */ + if (IS_VALLEYVIEW(dev)) + gmbus_set_freq(dev_priv); + I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); }