| Message ID | 1380095271-10016-1-git-send-email-chon.ming.lee@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Sep 25, 2013 at 03:47:51PM +0800, Chon Ming Lee wrote: > Fix the typo in previous commit for DP 1.62 divisor. > drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2 > > v2: sigh, the m1 div is 3. > > Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org> > Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> Ok, I'll try this one ... -Daniel
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5e1de35..a5e4e61 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = { static const struct dp_link_dpll vlv_dpll[] = { { DP_LINK_BW_1_62, - { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } }, + { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, { DP_LINK_BW_2_7, { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } };
Fix the typo in previous commit for DP 1.62 divisor. drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2 v2: sigh, the m1 div is 3. Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)