From patchwork Wed Sep 25 16:40:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 2943441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1BE57BFF05 for ; Wed, 25 Sep 2013 16:59:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B4DF20570 for ; Wed, 25 Sep 2013 16:59:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0638F2015E for ; Wed, 25 Sep 2013 16:59:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D695AE7CCC for ; Wed, 25 Sep 2013 09:59:05 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy7-pub.mail.unifiedlayer.com (oproxy7-pub.mail.unifiedlayer.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id E8C67E5CF8 for ; Wed, 25 Sep 2013 09:40:44 -0700 (PDT) Received: (qmail 28612 invoked by uid 0); 25 Sep 2013 16:40:41 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy7.mail.unifiedlayer.com with SMTP; 25 Sep 2013 16:40:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Message-Id:Date:Subject:To:From; bh=fWYBUy7zUW3SoYHeeX6TA9kFzvnIHzKT4NKHFwMWHso=; b=pPxmrHopqhSbV23UH1fz0rOFUpv5VTvDYfCwmUNYBCPZuzMNF+xlul33mcs7r3+UmWIZxfFXd7kUEKBkRD87/DezzR5hwZAGZnApXmtsowM7OCCdXWgbF0TJl7em5KrW; Received: from [67.161.37.189] (port=56391 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1VOs8n-00067x-6W for intel-gfx@lists.freedesktop.org; Wed, 25 Sep 2013 10:40:41 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Wed, 25 Sep 2013 09:40:40 -0700 Message-Id: <1380127240-1310-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.8.3.1 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH] drm/i915/vlv: hack to init backlight regs if BIOS fails to do so X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Still digging up the actual VBT info for this, but wanted to get this out there for testing, or in case others are also bugged by this. This can happen if you boot with an external display connected. In that case, the attached eDP backlight modulation frequency may not be programmed, so we need to use something (in this case the value my BIOS normally programs with just the internal display enabled). Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_panel.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 3bc89a6..a3536785 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -372,6 +372,9 @@ static u32 i915_read_blc_pwm_ctl(struct drm_device *dev) I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2); } + + if (IS_VALLEYVIEW(dev) && !val) + val = 0xffffffff; } return val; @@ -629,10 +632,24 @@ set_level: spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); } +/* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */ +static void intel_panel_init_backlight_regs(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (IS_VALLEYVIEW(dev)) { + u32 cur_val = I915_READ(BLC_PWM_CTL) & + ~BACKLIGHT_DUTY_CYCLE_MASK; + I915_WRITE(BLC_PWM_CTL, (0xf42 << 16) | cur_val); + } +} + static void intel_panel_init_backlight(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + intel_panel_init_backlight_regs(dev); + dev_priv->backlight.level = intel_panel_get_backlight(dev); dev_priv->backlight.enabled = dev_priv->backlight.level != 0; }