From patchwork Fri Sep 27 19:57:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 2956791 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 35F159F244 for ; Fri, 27 Sep 2013 19:59:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5BEFB20304 for ; Fri, 27 Sep 2013 19:59:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 65357202DD for ; Fri, 27 Sep 2013 19:59:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F181E826F for ; Fri, 27 Sep 2013 12:59:30 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy13-pub.mail.unifiedlayer.com (oproxy13-pub.mail.unifiedlayer.com [69.89.16.30]) by gabe.freedesktop.org (Postfix) with SMTP id 7CEFDE7B0B for ; Fri, 27 Sep 2013 12:57:29 -0700 (PDT) Received: (qmail 8309 invoked by uid 0); 27 Sep 2013 19:57:28 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy13.mail.unifiedlayer.com with SMTP; 27 Sep 2013 19:57:28 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=qerEh8MWcb5hzYDblQNBfykZQM3p7WLr4TMuKZ87euk=; b=cWKkkkFSeAF0eFIEl64oB8huA8tfdLYUdhI3GeF1hQy38GZyIHHtctDCOBsKsQGk+aCTCUoqOgRG83cbDeiHPH1YFT1+4XIz7XC3Q+T+Zq6HW7JtuRKesDZMEN9SiWwz; Received: from [67.161.37.189] (port=34187 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1VPeAJ-0007bs-VA for intel-gfx@lists.freedesktop.org; Fri, 27 Sep 2013 13:57:28 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Sep 2013 12:57:25 -0700 Message-Id: <1380311846-1581-4-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1380311846-1581-1-git-send-email-jbarnes@virtuousgeek.org> References: <1380311846-1581-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 4/5] drm/i915/vlv: untangle integrated clock source handling v2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The global integrated clock source bit resides in DPLL B on VLV, but we were treating it as a per-pipe resource. It needs to be set whenever any PLL is active, so pull setting the bit out of vlv_update_pll and into vlv_enable_pll. Also add a vlv_disable_pll to prevent disabling it when pipe B shuts down. I'm guessing on the references here, I expect this to bite any config where multiple displays are active or displays are moved from pipe to pipe. v2: re-add bits in vlv_update_pll to keep from confusing the state checker References: https://bugs.freedesktop.org/show_bug.cgi?id=67245 References: https://bugs.freedesktop.org/show_bug.cgi?id=69693 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9a83236..2c040cd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1387,6 +1387,13 @@ static void vlv_enable_pll(struct intel_crtc *crtc) if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) assert_panel_unlocked(dev_priv, crtc->pipe); + /* Make sure to use the integrated clock source */ + if (!crtc->pipe) + I915_WRITE(DPLL(1), I915_READ(DPLL(1)) | + DPLL_INTEGRATED_CRI_CLK_VLV); + else + dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; + I915_WRITE(reg, dpll); POSTING_READ(reg); udelay(150); @@ -1477,6 +1484,20 @@ static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) POSTING_READ(DPLL(pipe)); } +static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) +{ + u32 val = 0; + + /* Make sure the pipe isn't still relying on us */ + assert_pipe_disabled(dev_priv, pipe); + + /* Leave integrated clock source enabled for the other pipe */ + if (pipe) + val = I915_READ(DPLL(pipe)) & DPLL_INTEGRATED_CRI_CLK_VLV; + I915_WRITE(DPLL(pipe), val); + POSTING_READ(DPLL(pipe)); +} + void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) { u32 port_mask; @@ -3887,7 +3908,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) if (encoder->post_disable) encoder->post_disable(encoder); - if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) + if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) + vlv_disable_pll(dev_priv, pipe); + else if (!IS_VALLEYVIEW(dev)) i9xx_disable_pll(dev_priv, pipe); intel_crtc->active = false; @@ -4629,7 +4652,6 @@ static void vlv_update_pll(struct intel_crtc *crtc) DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; if (pipe) dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; - dpll |= DPLL_VCO_ENABLE; crtc->config.dpll_hw_state.dpll = dpll;