From patchwork Tue Oct 1 15:02:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 2970451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 24E90BFF0B for ; Tue, 1 Oct 2013 15:08:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D2E18203DB for ; Tue, 1 Oct 2013 15:08:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 368A52041F for ; Tue, 1 Oct 2013 15:08:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 143A1E75C5 for ; Tue, 1 Oct 2013 08:08:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 607EEE759A for ; Tue, 1 Oct 2013 08:02:42 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 01 Oct 2013 08:02:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.90,1013,1371106800"; d="scan'208"; a="409860966" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.167]) by fmsmga002.fm.intel.com with SMTP; 01 Oct 2013 08:02:27 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 01 Oct 2013 18:02:26 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Tue, 1 Oct 2013 18:02:10 +0300 Message-Id: <1380639741-5276-2-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1380639741-5276-1-git-send-email-ville.syrjala@linux.intel.com> References: <1380639741-5276-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/12] drm/i915: Set primary_disabled in intel_{enable, disable}_plane X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä If the primary gets marked as disabled while the pipe is off for instance, we should still re-enable it when the pipe is turned on, unless the sprite covers it fully also in that configuration. Unfortunately we do the plane visibility checks only in the sprite code, which is executed after the primary enabling when turning the pipe off. Ideally we should compute the plane visibility before touching the hardware at all, but for now just set the primary_disabld flag in intel_{enable,disable}_plane. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 29b9387..261e043 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1809,12 +1809,16 @@ void intel_flush_display_plane(struct drm_i915_private *dev_priv, static void intel_enable_plane(struct drm_i915_private *dev_priv, enum plane plane, enum pipe pipe) { + struct intel_crtc *intel_crtc = + to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); int reg; u32 val; /* If the pipe isn't enabled, we can't pump pixels and may hang */ assert_pipe_enabled(dev_priv, pipe); + intel_crtc->primary_disabled = false; + reg = DSPCNTR(plane); val = I915_READ(reg); if (val & DISPLAY_PLANE_ENABLE) @@ -1836,9 +1840,13 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, static void intel_disable_plane(struct drm_i915_private *dev_priv, enum plane plane, enum pipe pipe) { + struct intel_crtc *intel_crtc = + to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); int reg; u32 val; + intel_crtc->primary_disabled = true; + reg = DSPCNTR(plane); val = I915_READ(reg); if ((val & DISPLAY_PLANE_ENABLE) == 0)