From patchwork Sat Oct 5 04:22:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 2990791 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B471ABF924 for ; Sat, 5 Oct 2013 04:27:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AE061202C7 for ; Sat, 5 Oct 2013 04:27:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B54DE202C1 for ; Sat, 5 Oct 2013 04:27:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D8BCE6B4C for ; Fri, 4 Oct 2013 21:27:45 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 005DEE673B for ; Fri, 4 Oct 2013 21:23:03 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 04 Oct 2013 21:23:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.90,1037,1371106800"; d="scan'208"; a="411831726" Received: from unknown (HELO lundgren.intel.com) ([10.255.15.130]) by fmsmga002.fm.intel.com with ESMTP; 04 Oct 2013 21:23:03 -0700 From: Ben Widawsky To: Intel GFX Date: Fri, 4 Oct 2013 21:22:54 -0700 Message-Id: <1380946975-14431-6-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1380946975-14431-1-git-send-email-benjamin.widawsky@intel.com> References: <1380946975-14431-1-git-send-email-benjamin.widawsky@intel.com> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 6/7] drm/i915: Create GEN specific write MMIO X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Similar to the previous patch which implemented GEN specific reads; this patch does the same for writes. Writes have a bit of adding complexity due to the FPGA_DBG feature of HSW plus: gen[2-4]: nothing special gen5: ILK dummy write gen[6-7]: forcewake shenanigans gen[HSW}: forcewake shenanigans + FPGA_DBG I was a bit torn about whether or not to combine 6-HSW as one function, since the FPGA_DBG is cleanly separated, and it wouldn't make the 6-7 MMIO too messy. In the end, I chose the clearest possible solution which splits out HSW. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_uncore.c | 87 +++++++++++++++++++++++++++++++------ 1 file changed, 74 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index bcb4cfd..cd56212 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -408,16 +408,46 @@ __gen4_read(64) trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) -#define __i915_write(x) \ +#define __gen4_write(x) \ static void \ -i915_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ +gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ + REG_WRITE_HEADER; \ + __raw_i915_write##x(dev_priv, reg, val); \ + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ +} + +#define __gen5_write(x) \ +static void \ +gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ + REG_WRITE_HEADER; \ + ilk_dummy_write(dev_priv); \ + __raw_i915_write##x(dev_priv, reg, val); \ + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ +} + +#define __gen6_write(x) \ +static void \ +gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ + u32 __fifo_ret = 0; \ + REG_WRITE_HEADER; \ + if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ + __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ + } \ + __raw_i915_write##x(dev_priv, reg, val); \ + if (unlikely(__fifo_ret)) { \ + gen6_gt_check_fifodbg(dev_priv); \ + } \ + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ +} + +#define __hsw_write(x) \ +static void \ +hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ u32 __fifo_ret = 0; \ REG_WRITE_HEADER; \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ } \ - if (dev_priv->info->gen == 5) \ - ilk_dummy_write(dev_priv); \ hsw_unclaimed_reg_clear(dev_priv, reg); \ __raw_i915_write##x(dev_priv, reg, val); \ if (unlikely(__fifo_ret)) { \ @@ -427,11 +457,27 @@ i915_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ } -__i915_write(8) -__i915_write(16) -__i915_write(32) -__i915_write(64) -#undef __i915_write +__hsw_write(8) +__hsw_write(16) +__hsw_write(32) +__hsw_write(64) +__gen6_write(8) +__gen6_write(16) +__gen6_write(32) +__gen6_write(64) +__gen5_write(8) +__gen5_write(16) +__gen5_write(32) +__gen5_write(64) +__gen4_write(8) +__gen4_write(16) +__gen4_write(32) +__gen4_write(64) + +#undef __hsw_write +#undef __gen6_write +#undef __gen5_write +#undef __gen4_write #undef REG_WRITE_HEADER void intel_uncore_init(struct drm_device *dev) @@ -488,12 +534,27 @@ void intel_uncore_init(struct drm_device *dev) switch (INTEL_INFO(dev)->gen) { case 7: case 6: + if (IS_HASWELL(dev)) { + dev_priv->uncore.funcs.mmio_writeb = hsw_write8; + dev_priv->uncore.funcs.mmio_writew = hsw_write16; + dev_priv->uncore.funcs.mmio_writel = hsw_write32; + dev_priv->uncore.funcs.mmio_writeq = hsw_write64; + } else { + dev_priv->uncore.funcs.mmio_writeb = gen6_write8; + dev_priv->uncore.funcs.mmio_writew = gen6_write16; + dev_priv->uncore.funcs.mmio_writel = gen6_write32; + dev_priv->uncore.funcs.mmio_writeq = gen6_write64; + } dev_priv->uncore.funcs.mmio_readb = gen6_read8; dev_priv->uncore.funcs.mmio_readw = gen6_read16; dev_priv->uncore.funcs.mmio_readl = gen6_read32; dev_priv->uncore.funcs.mmio_readq = gen6_read64; break; case 5: + dev_priv->uncore.funcs.mmio_writeb = gen5_write8; + dev_priv->uncore.funcs.mmio_writew = gen5_write16; + dev_priv->uncore.funcs.mmio_writel = gen5_write32; + dev_priv->uncore.funcs.mmio_writeq = gen5_write64; dev_priv->uncore.funcs.mmio_readb = gen5_read8; dev_priv->uncore.funcs.mmio_readw = gen5_read16; dev_priv->uncore.funcs.mmio_readl = gen5_read32; @@ -502,16 +563,16 @@ void intel_uncore_init(struct drm_device *dev) case 4: case 3: case 2: + dev_priv->uncore.funcs.mmio_writeb = gen4_write8; + dev_priv->uncore.funcs.mmio_writew = gen4_write16; + dev_priv->uncore.funcs.mmio_writel = gen4_write32; + dev_priv->uncore.funcs.mmio_writeq = gen4_write64; dev_priv->uncore.funcs.mmio_readb = gen4_read8; dev_priv->uncore.funcs.mmio_readw = gen4_read16; dev_priv->uncore.funcs.mmio_readl = gen4_read32; dev_priv->uncore.funcs.mmio_readq = gen4_read64; break; } - dev_priv->uncore.funcs.mmio_writeb = i915_write8; - dev_priv->uncore.funcs.mmio_writew = i915_write16; - dev_priv->uncore.funcs.mmio_writel = i915_write32; - dev_priv->uncore.funcs.mmio_writeq = i915_write64; } void intel_uncore_fini(struct drm_device *dev)