| Message ID | 1381518570-6584-1-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2013/10/11 Jesse Barnes <jbarnes@virtuousgeek.org>: > On gen7+, CACHE_MODE_0 moved, so we're clobbering some other reg rather > than restoring CACHE_MODE_0. Don't do that. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_suspend.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > index 97ca8f1..98790c7 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -398,7 +398,8 @@ int i915_save_state(struct drm_device *dev) > intel_disable_gt_powersave(dev); > > /* Cache mode state */ > - dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > + if (INTEL_INFO(dev)->gen < 7) > + dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > > /* Memory Arbitration state */ > dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); > @@ -447,7 +448,9 @@ int i915_restore_state(struct drm_device *dev) > } > > /* Cache mode state */ > - I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); > + if (INTEL_INFO(dev)->gen < 7) > + I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | > + 0xffff0000); > > /* Memory arbitration state */ > I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Oct 11, 2013 at 05:09:57PM -0300, Paulo Zanoni wrote: > 2013/10/11 Jesse Barnes <jbarnes@virtuousgeek.org>: > > On gen7+, CACHE_MODE_0 moved, so we're clobbering some other reg rather > > than restoring CACHE_MODE_0. Don't do that. > > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> I really loathe our old legacy hw save/restore code - we always forget some random register here when enabling new generations. So hooray for this patch ;-) Both patches merged to dinq. -Daniel > > > --- > > drivers/gpu/drm/i915/i915_suspend.c | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > > index 97ca8f1..98790c7 100644 > > --- a/drivers/gpu/drm/i915/i915_suspend.c > > +++ b/drivers/gpu/drm/i915/i915_suspend.c > > @@ -398,7 +398,8 @@ int i915_save_state(struct drm_device *dev) > > intel_disable_gt_powersave(dev); > > > > /* Cache mode state */ > > - dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > > + if (INTEL_INFO(dev)->gen < 7) > > + dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > > > > /* Memory Arbitration state */ > > dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); > > @@ -447,7 +448,9 @@ int i915_restore_state(struct drm_device *dev) > > } > > > > /* Cache mode state */ > > - I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); > > + if (INTEL_INFO(dev)->gen < 7) > > + I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | > > + 0xffff0000); > > > > /* Memory arbitration state */ > > I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); > > -- > > 1.8.3.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 97ca8f1..98790c7 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -398,7 +398,8 @@ int i915_save_state(struct drm_device *dev) intel_disable_gt_powersave(dev); /* Cache mode state */ - dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); + if (INTEL_INFO(dev)->gen < 7) + dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); /* Memory Arbitration state */ dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); @@ -447,7 +448,9 @@ int i915_restore_state(struct drm_device *dev) } /* Cache mode state */ - I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); + if (INTEL_INFO(dev)->gen < 7) + I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | + 0xffff0000); /* Memory arbitration state */ I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
On gen7+, CACHE_MODE_0 moved, so we're clobbering some other reg rather than restoring CACHE_MODE_0. Don't do that. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/i915_suspend.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)