From patchwork Tue Oct 22 12:37:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 3082241 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5F7CC9F2B8 for ; Tue, 22 Oct 2013 12:37:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5712D2045E for ; Tue, 22 Oct 2013 12:37:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 43C0C20459 for ; Tue, 22 Oct 2013 12:37:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4BB8BE6BA2 for ; Tue, 22 Oct 2013 05:37:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f173.google.com (mail-ea0-f173.google.com [209.85.215.173]) by gabe.freedesktop.org (Postfix) with ESMTP id E735FE67E4 for ; Tue, 22 Oct 2013 05:37:36 -0700 (PDT) Received: by mail-ea0-f173.google.com with SMTP id g10so4224023eak.32 for ; Tue, 22 Oct 2013 05:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id; bh=/7554kZAPsdCh+DBXBIuTfIW1WjnGU+TfUvXs/jICaw=; b=PaCnXwEkFhaBNRbG7aatn8LjQxZL4wG6h3kXY7QFKgyOQ5Ui8oAyqjoAWQGGYSb/oI lUZqp1d3v0TLVmefcZ+H05yfWzyfTk6dixw6LiqkpMiUCOm1AtYByQDpqClBMck+6XMI 97nVg3OM2Vru10XmhTzFy78DiWFtV9QNImznY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=/7554kZAPsdCh+DBXBIuTfIW1WjnGU+TfUvXs/jICaw=; b=DO20BgximTPQfHNb7rAVvy+ErcdwKNEnJnufNWeOZykOhpgaHgRiXKyLfaI6ZLgxHt jOmjVMhw46qoPg+FJxqlK9xhldUuaUgQQVZcDvItrTDyFFVCLae8dpy8S4Awism4ENB+ Dc/BWqZVSyDFtGISfM5XHSmaegGDeSP17RTm9WBkjoCC37CrkxuMjDCoNZtGsIdKawwE nimSeLKfun7TSp/rndvXr40QobZ46Sc65vEjO3MGSJaQk5fEi5hY8EoI8Z3FHDQ4Ca19 5vPMc00S8H/jsjF1DwZNZzvmGi1REwzIKQ848mO5Q3Lv+OMSODSjiebzgje1J8gLUMMB 2i0Q== X-Gm-Message-State: ALoCoQkPwGdtY1d6FsN9yx39E4j8oAwYhsaBsCyESUZ1lXgVKyl+l4hf53idru0xXtsLNg+W9vdb X-Received: by 10.15.32.7 with SMTP id z7mr2296262eeu.78.1382445456021; Tue, 22 Oct 2013 05:37:36 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPSA id e47sm56373451eeo.8.2013.10.22.05.37.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Oct 2013 05:37:34 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 22 Oct 2013 14:37:53 +0200 Message-Id: <1382445473-17558-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.8.4.rc3 Cc: Daniel Vetter , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH] drm/i915: Sanitize the PPT fdi lane bifurcate state on ivb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We expect this bit to be always set when possible, but some BIOSes are lazy and don't do this. The result is a pile of WARNs and unhappy fdi link training code ... v2: It's actually the inverse: The BIOS sets this bit when it's not strictly needed. This should be cleaned up in the global_modeset_resources callback, but we've failed to look at the active bit. Which means this won't fire (and so clean up BIOS state) when enabling pipe B or C for the first time. v3: Wrap lines. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70507 Tested-by: Jan-Michael Brummer Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cfe9e709..3569db6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2421,9 +2421,10 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) FDI_FE_ERRC_ENABLE); } -static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) +static bool pipe_has_enabled_pch(struct intel_crtc *crtc) { - return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder; + return crtc->base.enabled && crtc->active && + crtc->config.has_pch_encoder; } static void ivb_modeset_global_resources(struct drm_device *dev)