| Message ID | 1383326394-3933-5-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Nov 01, 2013 at 07:19:50PM +0200, Imre Deak wrote: > Some upcoming platforms with power wells don't have this register, so > check for Haswell instead. > > Signed-off-by: Imre Deak <imre.deak@intel.com> The point of HAS_POWER_WELL was to make bdw work (for which we now have approval apparently). Depending upon how this all shapes out it's probably better to stall this series for a little bit until the bdw stuff has landed. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 8f40ae3..929ecce 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -11101,7 +11101,7 @@ intel_display_capture_error_state(struct drm_device *dev) > if (error == NULL) > return NULL; > > - if (HAS_POWER_WELL(dev)) > + if (IS_HASWELL(dev)) > error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); > > for_each_pipe(i) { > @@ -11171,7 +11171,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, > return; > > err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); > - if (HAS_POWER_WELL(dev)) > + if (IS_HASWELL(dev)) > err_printf(m, "PWR_WELL_CTL2: %08x\n", > error->power_well_driver); > for_each_pipe(i) { > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, 2013-11-01 at 20:41 +0100, Daniel Vetter wrote: > On Fri, Nov 01, 2013 at 07:19:50PM +0200, Imre Deak wrote: > > Some upcoming platforms with power wells don't have this register, so > > check for Haswell instead. > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > The point of HAS_POWER_WELL was to make bdw work (for which we now have > approval apparently). Depending upon how this all shapes out it's probably > better to stall this series for a little bit until the bdw stuff has > landed. Ok, rebasing this on top of the BDW stuff is minimal work. But comments on it would still be appreciated. --Imre
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8f40ae3..929ecce 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11101,7 +11101,7 @@ intel_display_capture_error_state(struct drm_device *dev) if (error == NULL) return NULL; - if (HAS_POWER_WELL(dev)) + if (IS_HASWELL(dev)) error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); for_each_pipe(i) { @@ -11171,7 +11171,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, return; err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); - if (HAS_POWER_WELL(dev)) + if (IS_HASWELL(dev)) err_printf(m, "PWR_WELL_CTL2: %08x\n", error->power_well_driver); for_each_pipe(i) {
Some upcoming platforms with power wells don't have this register, so check for Haswell instead. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)