From patchwork Sat Nov 2 00:02:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3129881 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F33BF9F474 for ; Sat, 2 Nov 2013 00:03:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D3088204A2 for ; Sat, 2 Nov 2013 00:03:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9B9A52049D for ; Sat, 2 Nov 2013 00:02:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A74D8F024B; Fri, 1 Nov 2013 17:02:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 76073EE90C for ; Fri, 1 Nov 2013 17:02:57 -0700 (PDT) Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga101.ch.intel.com with ESMTP; 01 Nov 2013 17:02:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,535,1378882800"; d="scan'208";a="315945627" Received: from jbrandeb-mobl.amr.corp.intel.com (HELO lundgren.intel.com) ([10.255.14.249]) by AZSMGA002.ch.intel.com with ESMTP; 01 Nov 2013 17:02:55 -0700 From: Ben Widawsky To: Intel GFX Date: Fri, 1 Nov 2013 17:02:52 -0700 Message-Id: <1383350573-7427-1-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.8.4.2 MIME-Version: 1.0 Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Fix fbc + rc6 combination on SNB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Sandybridge we must set the "PPGTT Render Target Base Address Valid for FBC" bit as noted in the programming guide. We did this at clock gating init. Thisbit is not saved and restored with RC6 power context, so the resetting it at ring flush should fix that. The effect of not doing this should be corruption, and not a hang - as has so often been the case. Note that we should actually clear this bit as well when not blitting to the scanout (using the blitter for other things), or else all operations Cc: Stéphane Marchesin Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_pm.c | 2 -- drivers/gpu/drm/i915/intel_ringbuffer.c | 25 +++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ca9a778..67f460b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -193,8 +193,6 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) /* Make sure blitter notifies FBC of writes */ gen6_gt_force_wake_get(dev_priv); blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); - blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << - GEN6_BLITTER_LOCK_SHIFT; I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2dec134..ddd7681 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -278,6 +278,28 @@ gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) return 0; } +static int gen6_ring_fbc_flush(struct intel_ring_buffer *ring) +{ + int ret; + + if (!ring->fbc_dirty) + return 0; + + ret = intel_ring_begin(ring, 4); + if (ret) + return ret; + + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(ring, GEN6_BLITTER_ECOSKPD); + intel_ring_emit(ring, + _MASKED_BIT_ENABLE(GEN6_BLITTER_FBC_NOTIFY)); + intel_ring_advance(ring); + + ring->fbc_dirty = false; + return 0; +} + static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) { int ret; @@ -1712,6 +1734,9 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); + if (IS_GEN6(dev) && flush) + return gen6_ring_fbc_flush(ring); + if (IS_GEN7(dev) && flush) return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);